b38c57d73b
firmware: send DRTIO routing table to satellite
2018-09-11 14:12:41 +08:00
3d29a7ed14
firmware: add fmt::Display to RoutingTable
2018-09-11 11:27:56 +08:00
31bef9918e
firmware: fix drtio_routing compatibility with master and satellite
2018-09-10 20:16:42 +08:00
7ae44f3417
firmware: add routing table (WIP)
2018-09-09 21:49:28 +08:00
87e0384e97
drtio: separate aux controller
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This helps with managing CSR groups and heterogeneous (satellite/repeaters) DRTIO cores.
2018-09-05 17:56:58 +08:00
d1d26e2aa3
hmc7043: add explanation about HMC_SYSREF_DIV
2018-08-18 11:43:40 +08:00
f75a317446
hmc7043: automatically determine output groups
2018-08-18 11:43:23 +08:00
c498b28f88
hmc7043: disable FPGA_ADC_SYSREF
2018-08-18 11:42:57 +08:00
167e97efd2
sayma: support external RTM clocking
2018-08-17 22:57:54 +08:00
5c3e834c4d
ad9154: retry DAC initialization on STPL or PRBS failure
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Works around #1127
2018-08-17 20:52:55 +08:00
738d2c6bcb
hmc7043: REFSYNCIN → RFSYNCIN
2018-08-11 12:07:17 +08:00
f7678cc24a
grabber: refactor state machine
2018-08-07 18:07:46 +02:00
6cd2432e30
grabber: log all resolution changes
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close #1120
2018-08-07 16:21:21 +02:00
99a15ca0c6
grabber: rationalize derived traits
2018-08-07 16:21:21 +02:00
49f7a1610f
sayma: use GTP_CLK1 only for all variants ( #1080 )
2018-08-07 20:53:14 +08:00
bbe36b94f7
ad9154: enable sync in init
2018-08-06 19:02:27 +08:00
7f0b2ff594
jesd204sync: work around HMC7043 poor behavior with combined delays
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The HMC7043 outputs poorly controlled signals when adjusting
two delays at once. This commit puts the DAC in one-shot SYSREF mode,
and only triggers synchronizations when SYSREF is stable.
2018-08-06 17:43:17 +08:00
f32f0126e2
Revert "ad9154: use continuous sync mode"
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The HMC7043 is not really glitchless.
This reverts commit bd968211de
2018-08-06 16:59:53 +08:00
bd968211de
ad9154: use continuous sync mode
2018-08-06 00:27:10 +08:00
e83ee3a07a
hmc7043: disable GTP_CLK1 when not in use
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Termination and biasing are not active at the FPGA when IBUFDS_GTE3 is
not instantiated, and driving a clock then leads to overvoltage.
2018-08-03 10:03:52 +08:00
446f791180
firmware: simplify SYSREF DRTIO alignment
2018-07-26 19:37:59 +08:00
32c95ac034
sayma: automated DAC SYSREF phase calibration
2018-07-26 16:23:55 +08:00
dbcf2fe9b4
firmware: remove 'chip found' messages on Sayma
2018-07-26 16:07:37 +08:00
d523d03f71
sayma: automated FPGA SYSREF phase offset calibration
2018-07-26 14:53:28 +08:00
19c51c644e
grabber: cleanup GRABBER_STATE
2018-07-24 19:08:51 +08:00
b27fa8964b
add variant in identifier string
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Also add without-sawg suffixes on Sayma.
Closes #1060
Closes #1059
2018-07-15 17:21:17 +08:00
46fb5adac3
grabber: fix frequency counter formula
2018-07-12 20:14:38 +08:00
82def6b535
grabber: add frequency counter
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Cameras are a bit obscure about what they output, this can help with troubleshooting.
2018-07-12 17:05:18 +08:00
29c35ee553
hmc7043: fix dumb mistake in previous commit
2018-07-12 13:01:41 +08:00
8802b930de
hmc7043: add delay after init
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Delay required at step 9 of the "Typical Programming Sequence" (page 24 of the datasheet)
2018-07-12 12:37:12 +08:00
c66f9483f8
hmc7043: wait after changing delays
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Allows for the SPI transaction to finish, and for the delay to stabilize.
2018-07-12 12:33:53 +08:00
773240bef4
hmc7043: test GPO before using
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Based on code by David.
2018-07-12 11:30:24 +08:00
4843832329
hmc7043: check phase status on init. Closes #1055
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Troubleshooting by David.
2018-07-11 19:45:24 +08:00
9397fa7f5a
hmc7043: unstick SYSREF FSM ( #1055 )
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Troubleshooting by David.
Additionally, register 7D is broken.
Checking phase init state has to be done through another means.
2018-07-11 19:11:01 +08:00
4f56710e4b
grabber: add parser, report detected frame size in core device log
2018-07-10 02:06:37 +08:00
4eb26c0050
hmc7043: enable group 5
2018-07-03 14:16:31 +02:00
a65721d649
sayma: put RTM clock tree into the siphaser loop
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* Fixes one bug where siphaser was one Si5324 output and the rest of the
system was clocked by the other. With the Si5324 settings we have, skew
between the outputs is not controlled.
* Puts the coaxial cable between AMC and RTM into the siphaser loop.
2018-06-27 21:46:55 +08:00
46c044099c
hmc7043,satman: verify alignment of SYSREF slips
2018-06-27 17:36:13 +08:00
7dfd70c502
hmc7043: make margin_{minus,plus} consistent with ad9154
2018-06-27 17:35:26 +08:00
4bbdd43bdf
hmc7043: do not freeze if SYSREF slip fails
2018-06-27 17:32:56 +08:00
76fc63bbf7
jesd204: use separate controls for reset and input buffer disable
2018-06-22 11:38:18 +08:00
de7d64d482
sayma: clock JESD204 from GTP CLK2
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This frees up GTP CLK1, which is routable to the SFP quads, for DRTIO.
2018-06-21 22:33:53 +08:00
07bcdfd91e
hmc7043: stricter check of FPGA SYSREF margin
2018-06-21 22:26:49 +08:00
5a2a857a2f
firmware: clean up SYSREF phase management
2018-06-21 16:23:41 +08:00
05e908a0fd
hmc7043: align SYSREF with RTIO
2018-06-21 15:54:42 +08:00
9741654cad
hmc7043: style
2018-06-21 15:54:42 +08:00
45e8263208
hmc7043: do not configure phases during initial init
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They are determined later on.
2018-06-21 15:54:42 +08:00
814d0583db
hmc7043: improve smoothness of sysref phase control
2018-06-20 17:40:48 +08:00
5272c11704
typo
2018-06-20 17:05:20 +08:00
0c32d07e8b
ad9154: new sysref scan
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Print margins around the pre-defined fixed phase.
Also report error if margins are too small.
The fixed phase is also changed by this commit (the value 88 is
from before the new HMC7043 initialization code, and is probably wrong).
2018-06-20 00:15:58 +08:00
