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969 Commits

Author SHA1 Message Date
Florent Kermarrec 73b727cade serwb: new version using only sys/sys4x clocks domains, scrambling deactivated. 2018-04-07 02:59:14 +02:00
Florent Kermarrec dd21c07b85 targets/sayma_rtm: fix serwb 2 ... 2018-04-03 18:59:05 +02:00
Florent Kermarrec 7488703f23 targets/sayma_rtm: fix serwb 2018-04-03 18:57:00 +02:00
Florent Kermarrec aef0153a8f targets/sayma: adapt to new serwb clocking 2018-04-03 18:53:39 +02:00
Florent Kermarrec 3248caa184 gateware/serwb: move all clocking outside of serwb, use existing sys/sys4x clocks 2018-04-03 18:48:08 +02:00
Sebastien Bourdeauducq f0771765c1 rtio: move CRI write comment to more appropriate location 2018-03-29 23:55:00 +08:00
Sebastien Bourdeauducq 493d2a653f siphaser: add false path between sys_clk and mmcm_freerun_output 2018-03-29 10:55:41 +08:00
Sebastien Bourdeauducq 4229c045f4 kasli: fix DRTIO master clock constraint 2018-03-29 10:20:31 +08:00
Sebastien Bourdeauducq 3d89ba2e11 sayma: remove debug leftover 2018-03-29 10:20:17 +08:00
Sebastien Bourdeauducq 605292535c kasli: ignore OSERDESE2->ISERDESE2 timing path on DRTIO targets as well 2018-03-29 10:12:02 +08:00
whitequark bab6723ff2 Revert "gateware: don't run tests if there is no migen." 
This reverts commit 4804cfef9b.
 2018-03-26 03:33:52 +00:00
whitequark 4804cfef9b gateware: don't run tests if there is no migen. 
This allows us to skip testing gateware on Windows.
 2018-03-26 03:26:34 +00:00
Robert Jördens 3a0dfb7fdc ad53xx: port monitor, moninj dashboard, kc705 target 2018-03-24 16:04:02 +01:00
Robert Jördens 1553fc8c7d sed: reset `valid` in output sorter 2018-03-23 11:11:11 +00:00
Robert Jördens 770b0a7b79 novogorny: conv -> cnv 
* parity with sampler
* also add novogorny device to opticlock
 2018-03-21 18:38:42 +00:00
Robert Jördens 1afce8c613 kasli: simplify single eem pin formatting 2018-03-21 13:08:42 +01:00
Robert Jördens d48b8f3086 kasli: fix sampler sdr/cnv pins 2018-03-21 09:28:00 +00:00
Robert Jördens 1fb5907362 kasli: add SUServo variant (Sampler-Urukul Servo) 2018-03-21 08:53:26 +00:00
Robert Jördens f74d5772f4 sampler: add wide eem definition 2018-03-21 08:53:26 +00:00
Sebastien Bourdeauducq 32f22f4c9c sayma: disable SERDES TTL entirely 
Timing closure becomes very random, even at 4X.
 2018-03-21 13:03:48 +08:00
Sebastien Bourdeauducq f8c2d54e75 ttl_serdes_ultrascale: configurable SERDES ratio. Also try X4 on Sayma 2018-03-21 13:01:38 +08:00
Sebastien Bourdeauducq 9c2d343052 sayma: use SERDES RTIO TTL 
This is not enabled on the standalone design as it breaks timing.
 2018-03-21 10:53:52 +08:00
Sebastien Bourdeauducq c8020f6bbd ttl_serdes_generic: fix/upgrade test 2018-03-20 16:46:57 +08:00
Sebastien Bourdeauducq a5825184b7 add ttl_serdes_ultrascale (untested) 2018-03-20 16:07:23 +08:00
Sebastien Bourdeauducq fad066f1aa ttl_serdes_7series: cleanup indentation 
Inconsistent with other code and confuses text editors.
 2018-03-20 15:50:04 +08:00
Thomas Harty 37d431039d Fix typos. 
Reduce ififo depth to 4 for Zotino.
 2018-03-19 09:42:18 +00:00
Thomas Harty c4fa44bc62 Add Zotino and Sampler functions to Kasli. Add Zotino to Kasli EEM 7 on OptiClock. 2018-03-18 00:25:43 +00:00
Sebastien Bourdeauducq a315ecd10b rtio/ttl_serdes_7series: reset IOSERDES (#958) 2018-03-14 09:01:29 +08:00
Robert Jördens 2fdc180601 dsp/fir: outputs reset_less (pipelined) 2018-03-13 17:11:50 +00:00
Sebastien Bourdeauducq 2edf65f57b drtio: fix satellite minimum_coarse_timestamp clock domain (#947) 2018-03-13 00:20:57 +08:00
Sebastien Bourdeauducq 1d081ed6c2 drtio: print diagnostic info on satellite write underflow (#947) 2018-03-12 23:41:19 +08:00
Florent Kermarrec eb6e59b44c sayma_rtm: fix serwb timing constraints (was causing the gated clock warning) 2018-03-12 11:25:29 +01:00
Chris Ballance 6dfebd54dd ttl_serdes_7series: use correct IBUFDS_INTERMDISABLE port names 2018-03-12 10:37:33 +08:00
Sebastien Bourdeauducq fc3d97f1f7 drtio: remove spurious multichannel transceiver clock constraints 
They used to cause (otherwise harmless) Vivado critical warnings.
 2018-03-09 22:46:27 +08:00
Sebastien Bourdeauducq caf7b14b55 kasli: generate fine RTIO clock in DRTIO targets, separate RTIO channel code 2018-03-09 22:36:16 +08:00
Sebastien Bourdeauducq 3fbcf5f303 drtio: remove TSC correction (#40) 2018-03-09 10:36:17 +08:00
Sebastien Bourdeauducq e38187c760 drtio: increase default underflow margin. Closes #947 2018-03-09 00:49:24 +08:00
Sebastien Bourdeauducq 8bd15d36c4 drtio: fix error CSR edge detection (#947) 2018-03-08 16:28:25 +08:00
Robert Jördens 82831a85b6 kasli/opticlock: add eem6 phys 2018-03-07 21:32:59 +01:00
Robert Jördens 3a6566f949 rtio: judicious spray with reset_less=True 
Hoping to reduce rst routing difficulty and easier RTIO timing closure.
 2018-03-07 14:57:18 +00:00
Robert Jördens b0282fa855 spi2: reset configuration in rio_phy 2018-03-07 14:42:11 +00:00
Robert Jördens 4af7600b2d Revert "LaneDistributor: try equivalent spread logic" 
This reverts commit 8b70db5f17.

Just a shot into the dark.
 2018-03-07 11:34:51 +00:00
Robert Jördens a6d1b030c1 RTIO: use TS counter in the correct CD 
artiq/m-labs#938
 2018-03-07 11:34:42 +00:00
Robert Jördens 8b70db5f17 LaneDistributor: try equivalent spread logic 2018-03-07 11:34:42 +00:00
Robert Jördens 2cbd597416 LaneDistributor: style and signal consolidation [NFC] 2018-03-07 11:34:42 +00:00
Sebastien Bourdeauducq 916197c4d7 siphaser: cleanup 2018-03-07 11:15:44 +08:00
Sebastien Bourdeauducq f7aba6b570 siphaser: fix phase_shift_done CSR 2018-03-07 10:57:30 +08:00
Sebastien Bourdeauducq acfd9db185 siphaser: minor cleanup 2018-03-07 10:57:30 +08:00
Sebastien Bourdeauducq 7d98864b31 sayma: enable siphaser 2018-03-07 10:57:30 +08:00
Sebastien Bourdeauducq a6e29462a8 sayma: enable multilink DRTIO 2018-03-07 10:57:30 +08:00
Sebastien Bourdeauducq c34d00cbc9 drtio: implement Si5324 phaser gateware and partial firmware support 2018-03-07 10:57:30 +08:00
Robert Jördens 994ceca9ff sayma_amc: disable slave fpga gateware loading 2018-03-06 17:27:43 +01:00
Robert Jördens 62af7fe2ac Revert "kasli/opticlock: use plain ttls for channels 8-23" 
This reverts commit bd5c222569eb68d624a5ac1e9f2542f6ee553f83.

No decrease in power consumption or improvement in timing.
 2018-03-06 14:27:19 +01:00
Robert Jördens fd3cdce59a kasli/opticlock: use plain ttls for channels 8-23 2018-03-06 14:27:19 +01:00
Robert Jördens 50298a6104 ttl_serdes_7series: suppress diff_term in outputs 2018-03-06 14:27:19 +01:00
Robert Jördens e356150ac4 ttl_simple: support differential io 2018-03-06 14:27:19 +01:00
Robert Jördens 956098c213 kasli: add second urukul, make clk_sel drive optional 2018-03-06 14:26:27 +01:00
Robert Jördens 07de7af86a kasli: make second eem optional in urukul 2018-03-06 14:26:26 +01:00
Sebastien Bourdeauducq c25560baec sed: more LaneDistributor comments 2018-03-06 20:56:35 +08:00
Sebastien Bourdeauducq f40255c968 sed: add comments about key points in LaneDistributor 2018-03-06 20:51:09 +08:00
Florent Kermarrec 5b3d6d57e2 drtio/gth: power down rx on restart (seems to make link initialization reliable) 2018-03-06 11:49:28 +01:00
Florent Kermarrec 64b05f07bb drtio/gth: use parameters from Xilinx transceiver wizard 2018-03-06 11:02:15 +01:00
Florent Kermarrec 45f1e5a70e drtio/gth: cleanup import 2018-03-06 10:56:07 +01:00
Sebastien Bourdeauducq 6aaa8bf9d9 drtio: fix link error generation 2018-03-04 23:20:13 +08:00
Sebastien Bourdeauducq d747d74cb3 test: fix test_dma 2018-03-04 23:19:06 +08:00
Sebastien Bourdeauducq 928d5dc9b3 drtio: raise RTIOLinkError if operation fails due to link lost (#942) 2018-03-04 01:02:53 +08:00
Robert Jördens ddcc68cff9 sayma_amc: move bitstream options to migen 
close #930
 2018-03-02 18:13:03 +08:00
Sebastien Bourdeauducq a9daaad77b kasli: add SYSU variant and device_db 2018-03-02 14:44:31 +08:00
Robert Jördens cc70578f1f remove old spi RTIO Phy 2018-03-01 11:19:18 +01:00
Robert Jördens ec5b81da55 kc705: switch backplane spi to spi2 2018-03-01 11:19:18 +01:00
Robert Jördens a7720d05cd firmware, sayma: port converter_spi to spi2 
* ksupport/nrt_bus
* port ad9154, hmc830, hmc7043
* port local_spi and drtio_spi
* port kernel_proto libdrtioaux, satman
* change sayma_rtm gateware over
* add spi2 NRTSPIMaster
* remove spi NRTSPIMaster
* change sayma device_db
* change HMC830 to open mode and explicitly sequence open mode
 2018-03-01 11:19:18 +01:00
Robert Jördens 54984f080b artiq_flash: flash RTM firmware 
based on whitequark's work in f95fb27

m-labs/artiq#813
 2018-02-28 19:29:01 +01:00
Robert Jördens 1f999c7f5f sayma_amc: expose RTM fpga load pins as GPIOs 2018-02-28 18:44:36 +01:00
Florent Kermarrec 2896dc619b drtio/transceiver/gth: fix multilane 2018-02-28 14:15:40 +01:00
Sebastien Bourdeauducq 386aa75aaa kasli: control SFP1 and SFP2 LEDs in DRTIO satellite to match master 2018-02-27 23:18:18 +08:00
Sebastien Bourdeauducq 5d81877b34 kasli: implement multi-link DRTIO on SFP1 and SFP2 of master 2018-02-27 23:15:20 +08:00
Florent Kermarrec 1f0d955ce4 drtio/transceiver/gtp: implement tx multi lane phase alignment sequence 2018-02-27 12:32:25 +01:00
Sebastien Bourdeauducq e565d3fa59 kasli: add analyzer and RTIO log to DRTIO master target 2018-02-27 18:09:07 +08:00
Florent Kermarrec 5b0f9cc6fd drtio/transceiver/gth: fix single transceiver case 2018-02-23 12:15:47 +01:00
Florent Kermarrec b4ba71c7a4 drtio/transceiver/gth: implement tx multi lane phase alignment sequence (fix merge issue...) 2018-02-23 08:37:05 +01:00
Florent Kermarrec 820c834251 drtio/transceiver/gth: implement tx multi lane phase alignment sequence 2018-02-22 22:14:15 +01:00
Robert Jördens 1452cd7447 novogorny: add coredevice driver and test with Kasli 
m-labs/artiq#687
 2018-02-22 17:19:51 +01:00
Robert Jördens 3b7971d15d kasli: spelling 2018-02-22 17:19:51 +01:00
Robert Jördens 771bf87b56 kc705: port amc101_dac/spi0 and sma_spi to spi2 2018-02-22 17:19:51 +01:00
Robert Jördens f8e6b4f4e3 ad5360: port to spi2 
* kc705 nist_clock target gateware
* coredevice driver
* moninj code
* test/example/device_db

This is untested as we don't have a AD5360 board right now.
Will be tested with Zotino v1.1

m-labs/artiq#926
 2018-02-22 10:25:46 +01:00
Sebastien Bourdeauducq fa0d929b4d drtio: reorganize RX synchronizers 2018-02-22 15:21:23 +08:00
Sebastien Bourdeauducq e5de5ef473 kasli: use deterministic RX synchronizer 
Could not reproduce the "fully broken bitstream" bug.
 2018-02-22 15:18:09 +08:00
Robert Jördens a5ad1dc266 kc705: fix sdcard miso pullup 2018-02-21 19:41:05 +01:00
Robert Jördens 0d8145084d test_spi: move to new spi2 core 2018-02-21 19:41:05 +01:00
Robert Jördens a63fd306af urukul: use spi2 
* switch kc705 and kasli targets to spi2 gateware on urukul
* rewrite urukul, ad9912, ad9910
* update example experiments, device_dbs
 2018-02-21 15:00:28 +00:00
Robert Jördens 37a0d6580b spi2: add RTIO gateware and coredevice driver 
1006218997
 2018-02-21 13:37:36 +00:00
Robert Jördens 91a4a7b0ee kasli: free run si5324 on opticlock for now 2018-02-21 13:37:29 +00:00
Robert Jördens 7a1d71502a ttl_serdes_7series: drive IBUF and INTERM disables from serdes 2018-02-21 13:37:29 +00:00
Robert Jördens 476e4fdd56 ttl_serdes_7series: disable IBUF and INTERM when output 2018-02-21 13:37:29 +00:00
Sebastien Bourdeauducq f060d6e1b3 drtio: increase A7 clock aligner check period 2018-02-20 18:50:35 +08:00
Sebastien Bourdeauducq f15b4bdde7 style 2018-02-20 18:47:59 +08:00
Sebastien Bourdeauducq 7d9c7ada71 drtio: fix test infinite loop 2018-02-20 17:42:00 +08:00
Sebastien Bourdeauducq ad2c9590d0 drtio: rewrite/fix reset and link bringup/teardown 2018-02-20 17:26:43 +08:00
Robert Jördens 7e02d8245c kasli: false paths 
* don't bother with the round trip OSERDESE2 -> ... -> pad -> ... ->
  ISERDESE2
* clock groups with derived clocks c.f. migen 9c3a301
 2018-02-19 13:05:11 +00:00
Sebastien Bourdeauducq 0f4549655b sayma: use Xilinx RX synchronizer 
Cannot be used on Kasli, this breaks the bitstream entirely (nothing on UART).
 2018-02-19 17:49:53 +08:00