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23 Commits

Author SHA1 Message Date
Robert Jördens 2fdc180601 dsp/fir: outputs reset_less (pipelined) 2018-03-13 17:11:50 +00:00
Robert Jördens 600a48ac61 dsp.fir: cleanup 2017-06-29 12:18:48 +02:00
Robert Jördens dca662a743 dsp.fir: pipeline final systolic adder 2017-06-29 11:33:19 +02:00
Robert Jördens 32a33500c8 dsp.fir: actively cull zero delays 2017-06-29 11:24:56 +02:00
Robert Jördens 6bb994228f dsp.fir: drop x shift 2017-06-28 19:55:15 +02:00
Robert Jördens b9859cc0c3 dsp.fir: remove old/wrong comment 2017-06-28 19:21:57 +02:00
Robert Jördens 55b5b87490 fir: simplify latency compensation 
Don't try to tweak out the last bit of latency by feeding the HBF input
early. Instead feed it late so the interpolated samples are early and
the latency is an even multiple of the super-sample cycle.
 2017-06-28 19:13:43 +02:00
Robert Jördens 6418205906 dsp.fir: use pipelin-reset 2017-06-28 19:09:21 +02:00
Robert Jördens 1fb3995ffc Revert "fir/ParallelHBFUpsampler: add headroom (gain=2)" 
This reverts commit 6ac9d0c41e.

Overshooting behavior must to be handled outside the FIR.
 2017-06-12 20:07:25 +02:00
Robert Jördens 332bcc7f3b fir: check widths 2017-06-12 20:07:23 +02:00
Robert Jördens 6ac9d0c41e fir/ParallelHBFUpsampler: add headroom (gain=2) 
This addresses part of #743
 2017-06-12 18:59:45 +02:00
Robert Jördens f5f662200b fir: streamline, optimize DSP extraction, left-align inputs 2016-12-20 21:39:51 +01:00
Robert Jördens cfb66117af fir: size hint for pre-adder 2016-12-20 17:58:06 +01:00
Robert Jördens f310274e39 fir: cleanup halfgen4 2016-12-20 17:58:06 +01:00
Robert Jördens 115ea67860 fir: automatically use transposed topology 2016-12-14 19:16:07 +01:00
Robert Jördens a451b675c9 Revert "fir: different adder layout" 
This reverts commit 6f50e77b409c293c1905f28e69d79403a0803866.
 2016-12-14 19:16:07 +01:00
Robert Jördens 93076b8efa fir: different adder layout 2016-12-14 19:16:07 +01:00
Robert Jördens 61abd994e9 Revert "fir: force dsp48" 
This reverts commit 0ad433832d1b6dcd803ffa086ae73b2ee0568326.
 2016-12-14 19:16:07 +01:00
Robert Jördens 641d109786 fir: force dsp48 2016-12-14 19:16:07 +01:00
Robert Jördens b7a308d33d fir: register multiplier output 2016-12-08 17:00:39 +01:00
Robert Jördens a629eb1665 fir: add ParallelHBFCascade 2016-12-08 15:30:26 +01:00
Robert Jördens d303225249 fir: add ParallelFIR and test 2016-12-08 15:21:04 +01:00
Robert Jördens 7e0f3edca5 gateware/dsp: add FIR and test 2016-12-07 19:14:23 +01:00