David Nadlinger
4f311e7448
compiler: Raise exception on failed assert()s rather than panic
...
This allows assert() to be used on Zynq, where abort() is not
currently implemented for kernels. Furthermore, this is arguably
the more natural implementation of assertions on all kernel targets
(i.e. where embedding into host Python is used), as it matches host
Python behavior, and the exception information actually makes it to
the user rather than leading to a ConnectionClosed error.
Since this does not implement printing of the subexpressions, I
left the old print+abort implementation as default for the time
being.
The lit/integration/instance.py diff isn't just a spurious change;
the exception-based assert implementation exposes a limitation in
the existing closure lifetime tracking algorithm (which is not
supposed to be what is tested there).
GitHub: Fixes #1539 .
2020-11-10 00:51:24 +01:00
Etienne Wodey
ecef5661ce
coredevice/phaser: fix typos in docstring
...
Signed-off-by: Etienne Wodey <wodey@iqo.uni-hannover.de>
2020-10-29 20:27:08 +01:00
eecd97ce4c
phaser: debug and comments
2020-09-27 17:15:16 +00:00
c453c24fb0
phaser: tweak slacks
2020-09-26 21:16:08 +00:00
6c8bddcf8d
phaser: tune sync_dly
2020-09-26 21:13:00 +00:00
569e5e56cd
phaser: autotune and fix fifo_offset
2020-09-26 20:37:16 +00:00
2fba3cfc78
phaser: debug init, systematic bring-up
2020-09-25 20:54:59 +00:00
fec2f8b763
phaser: increase slack for iotest
2020-09-24 10:59:22 +00:00
6e6480ec21
phaser: tweak slacks and errors, identify trf
2020-09-24 08:38:30 +00:00
03d5f985f8
phaser: another artiq-python signed integer quirk
2020-09-23 15:40:54 +00:00
ef65ee18bd
dac34h84: unflip spectrum, clear nco
2020-09-23 08:35:56 +00:00
50b4eb4840
Merge branch 'master' into phaser
...
* master: (26 commits)
fastino: documentation and eem pass-through
kasli2: forward sma_clkin to si5324
test: relax test_dma_playback_time on Zynq
rpc: fixed _write_bool
fastino: document/cleanup
build_soc: remove assertion that was used for test runs
metlino_sayma_ttl: Fix RTIO frequency & demo code (#1516 )
Revert "test: temporarily disable test_async_throughput"
build_soc: rename identifier_str to gateware_identifier_str
test: relax loopback gate timing
test: temporarily disable test_async_throughput
test: relax test_pulse_rate on Zynq
test: skip NonexistentI2CBus if I2C is not supported
build_soc: override identifier_str only for gateware
examples: add Metlino master, Sayma satellite with TTLOuts via FMC
sayma_amc: add support for 4x DIO output channels via FMC
fmcdio_vhdci_eem: fix pin naming
build_soc: add identifier_str override option
RPC: optimization by caching
test: improved test_performance
...
2020-09-22 16:02:25 +00:00
c55f2222dc
fastino: documentation and eem pass-through
...
* Repeat information about matching log2_width a few times
in the hope that people read it. #1518
* Pass through log2_width in kasli_generic json. close #1481
* Check DAC value range. #1518
2020-09-22 17:58:53 +02:00
85d16e3e5f
phaser: tweaks
2020-09-22 15:27:38 +00:00
fd5e221898
phaser: dac and trf register maps, init code
2020-09-22 14:08:39 +00:00
3e036e365a
phaser: nco, settings and init tweaks
2020-09-22 09:52:49 +00:00
fdb2867757
phaser: fewer iotest patterns
2020-09-21 17:06:26 +02:00
d730851397
phaser: elaborate init sequence, more tests
2020-09-21 15:05:29 +00:00
f0959fb871
phaser: iotest early, check_alarms
2020-09-17 14:13:58 +00:00
b15e388b5f
ad53xx: distinguish errors
2020-09-17 14:13:10 +00:00
c18f515bf9
phaser: rework rtio channels, sync_dly, init()
2020-09-16 12:23:07 +00:00
f3b0398720
phaser: n=2, m=16, sync_dly
2020-09-16 09:19:15 +00:00
9b58b712a6
phaser: doc tweaks
2020-09-15 12:35:26 +00:00
ff57813a9c
phaser: init [wip]
2020-09-15 08:46:47 +00:00
07418258ae
phaser: init [wip]
2020-09-15 08:46:10 +00:00
3a79ef740b
phaser: work around integer size
2020-09-15 08:46:10 +00:00
b449e7202b
phaser: rework docs
2020-09-15 08:46:10 +00:00
b619f657b9
phaser: doc tweaks
2020-09-12 19:59:49 +02:00
c3728678d6
phaser: document, elaborate comments, some fixes
2020-09-12 17:35:14 +00:00
e505dfed5b
phaser: refactor coredevice driver
2020-09-12 14:17:40 +00:00
fdd2d6f2fb
phaser: SI methods
2020-09-12 11:02:37 +00:00
e69bb0aeb3
phaser: add comment about get_dac_data
2020-09-07 16:06:16 +00:00
6195b1d3a0
rpc: fixed _write_bool
...
Closes #1519
2020-09-04 13:49:22 +08:00
56aa22caeb
fastino: document/cleanup
...
* added documentation on `update`/`hold` mechanism
* mask machine unit values
* cleanup coredevice driver
close #1518
2020-09-03 17:44:26 +02:00
272dc5d36a
phaser: documentation
2020-08-28 16:36:44 +00:00
b2572003ac
RPC: optimization by caching
...
This reduced the calls needed for socket send/recv.
2020-08-28 14:58:34 +08:00
7cf974a6a7
comm_kernel: fix typo
2020-08-28 12:25:23 +08:00
68bfa04abb
phaser: trf readback strobe spi changes
2020-08-27 15:31:42 +00:00
c10ac2c92a
phaser: add trf, duc, interfaces, redo body assembly, use more natrual iq ordering (i lsb)
2020-08-27 14:26:09 +00:00
e5e2392240
phaser: wire up multidds
2020-08-26 17:12:41 +00:00
d1be1212ab
phaser: coredevice shim, dds [wip]
2020-08-26 15:10:50 +00:00
7181ff66a6
compiler: improved rpc performance for list and array
...
1. Removed duplicated tags before each elements.
2. Use numpy functions to speedup parsing.
2020-08-26 14:17:06 +08:00
20fcfd95e9
phaser: coredevice shim, readback fix
2020-08-24 15:46:31 +00:00
David Nadlinger
8783ba2072
compiler/firmware: RPCs for ndarrays
2020-08-09 17:08:43 +01:00
David Nadlinger
9af6e5747d
compiler: Factor rpc_tag() out of llvm_ir_generator
2020-08-09 03:54:41 +01:00
pmldrmota
1df62862cd
AD9910: Write correct number of bits to POW register ( #1498 )
...
* coredevice.ad9910: Add return type hints to conversion functions
* coredevice.ad9910: Make set_pow write correct number of bits
The AD9910 expects 16 bits. Thus, if writing 32 bits to the POW register, the chip would likely enter a locked-up state.
* coredevice.ad9910: Correct data alignment in write_16
Co-authored-by: Robert Jördens <rj@quartiq.de>
* coredevice.ad9910: Add function to read from 16 bit registers
Co-authored-by: drmota <peter.drmota@physics.ox.ac.uk>
Co-authored-by: Robert Jördens <rj@quartiq.de>
2020-08-07 10:10:44 +02:00
2a2f5c4d58
comm_analyzer: make header error flag more general
2020-07-20 19:39:19 +08:00
charlesbaynham
2429a266f6
ad9912: Fix typing problem on ad9912 ( #1466 )
...
Closes #1463
FTW and phase word were ambiguously typed, resulting in failure to compile
2020-06-16 20:17:22 +02:00
9822b88d9b
ad9910: fix asf range ( #1450 )
...
* ad9910: fix asf range
The ASF is a 14-bit word. The highest possible value is 0x3fff, not
0x3ffe. `int(round(1.0 * 0x3fff)) == 0x3fff`.
I don't remember and understand why this was 0x3ffe since the beginning.
0x3fff was already used as a default in `set_mu()`
Signed-off-by: Robert Jördens <rj@quartiq.de>
* RELEASE_NOTES: ad9910 asf scale change
Co-authored-by: David Nadlinger <code@klickverbot.at>
2020-05-29 11:13:26 +02:00
2538840756
Coredevice Input Validation ( #1447 )
...
* Input validation and masking of SI -> mu conversions (close #1446 )
Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>
* Update RELEASE_NOTES
Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>
Co-authored-by: Robert Jördens <rj@quartiq.de>
2020-05-17 15:09:11 +02:00
b3b6cb8efe
ad53xx improvements ( #1445 )
...
* ad53xx: voltage_to_mu() validation & documentation (closes #1443 , #1444 )
The voltage input (float) is checked for validity. If we need more
speed, we may want to check the DAC-code for over/underflow instead.
Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>
* ad53xx documentation: voltage_to_mu is only valid for 16-bit DACs
Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>
* AD53xx: add voltage_to_mu method (closes #1341 )
Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>
* ad53xx: improve voltage_to_mu performance
Interger comparison is faster than floating point math.
Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>
* AD53xx: voltage_to_mu method now uses attribute values
Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>
* Fixup RELEASE_NOTES.rst
Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>
* ad53xx: documentation improvements
voltage_to_mu return value
14-bit DAC support
Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>
2020-05-08 19:23:43 +02:00
e8b73876ab
comm_kernel: add Zynq runtime identifier
2020-04-12 17:25:14 +08:00
de57039e6e
comm_kernel: cleanup
2020-04-12 16:02:36 +08:00
9dc24f255e
comm_kernel: remove dead code
2020-04-12 15:06:46 +08:00
e803830b3b
fastino: support wide RTIO interface and channel groups
2020-03-05 17:55:04 +00:00
8451e58fbe
ad9912: fix ftw width docstring
2020-02-27 02:11:12 +08:00
248230a89e
fastino: style
2020-01-20 13:25:00 +01:00
c45a872cba
fastino: fix init, set_cfg
2020-01-20 13:25:00 +01:00
2c4e5bfee4
fastino: add [WIP]
2020-01-20 13:25:00 +01:00
e427aaaa66
basemod_att: fix imports
2020-01-20 20:14:24 +08:00
7ab0282234
adf5355: style
2020-01-20 13:13:08 +01:00
9368c26d1c
mirny: add to manual
2020-01-20 13:13:08 +01:00
01a6e77d89
mirny: add
...
* This targets unrelease CPLD gateware (https://github.com/quartiq/mirny/issues/1 )
* includes initial coredevice driver, eem shims, and kasli_generic tooling
* addresses the ARTIQ side of #1130
* Register abstraction to be written
Signed-off-by: Robert Jördens <rj@quartiq.de>
2020-01-20 13:13:08 +01:00
833f428391
sayma: fix hmc542 to/from mu
2020-01-16 09:10:32 +08:00
David Nadlinger
1e864b7e2d
coredevice/suservo: Add separate methods for setting only the IIR offset
2019-12-30 20:02:22 +00:00
b5e1bd3fa2
coredevice: simplify/cleanup network connection code
...
This removes:
* host-side keepalive, which turns out not to be required
* custom connection timeout (the default is OK)
* SSH tunneling support (doesn't seem to be actually used anywhere)
2019-12-23 19:53:49 +08:00
David Nadlinger
af31c6ea21
coredevice: Don't use is to compare with integer literal
...
This works on CPython, but is not guaranteed to do so, and
produces a warning since 3.8 (see https://bugs.python.org/issue34850 ).
2019-12-22 05:46:41 +00:00
fb2076a026
basemod_att: add dB functions, document
2019-12-21 14:56:41 +08:00
d4e039cede
basemod: add coredevice driver
2019-12-21 14:18:10 +08:00
8759c8d360
shiftreg: fix get method
2019-12-21 14:17:22 +08:00
cab8c8249e
coredevice/shiftreg: add get method
2019-12-20 18:58:50 +08:00
gthickman
56d4b70e01
ad9910 osk ( #1387 )
...
* updated adoo10.py for RAM mode frequency control
* updated docstrings for set_cfr1() in ad9910.py
* fixed typo in ad9910.py
* added docstrings to ad9910.py
* removed OSK-related changes in AD9910, to be included in a separate branch.
* updated AD9910 set_cfr1 for control of OSK mode parameters
* updated AD9910 set_cfr1() for control of OSK mode parameters.
2019-11-18 15:57:26 +01:00
Fabian Schmid
f73e2a3d30
doc: clarify urukul attenuator behavior
...
Closes #1386
Signed-off-by: Fabian Schmid <fabian.schmid@mpq.mpg.de>
2019-11-18 15:56:00 +01:00
Garrett
f8a7e278b8
removed OSK-related changes in AD9910, to be included in a separate branch.
2019-11-12 19:07:05 +01:00
Garrett
3a19ba7e62
added docstrings to ad9910.py
2019-11-12 19:07:05 +01:00
Garrett
4ad3651022
fixed typo in ad9910.py
2019-11-12 19:07:05 +01:00
Garrett
6d34eb3bb0
updated docstrings for set_cfr1() in ad9910.py
2019-11-12 19:07:05 +01:00
Garrett
61ca46ec3f
updated adoo10.py for RAM mode frequency control
2019-11-12 19:07:05 +01:00
5279bc275a
urukul: rework EEPROM synchronization. Closes #1372
2019-11-05 18:56:10 +08:00
1f15e55021
comm_analyzer: don't assume every message has data
...
close #1377
2019-10-28 15:35:44 +01:00
a8f85860c4
coreanalyzer: AD9914 fixes ( #1376 )
2019-10-17 07:29:33 +08:00
Tim Ballance
ada3b39f4e
Fix ad9910 ram mode asf scale error in polar mode
2019-10-04 20:14:41 +02:00
Tim Ballance
448080e71d
Fix ad9910 ram mode asf scale error
...
RAM mode amplitude to ASF conversion should be << 18 rather than << 16
2019-10-04 20:14:41 +02:00
98cd9a539c
compiler: support Cortex A9 target
2019-08-26 10:46:22 +08:00
David Nadlinger
99e490f9ff
coredevice/suservo: Slightly reword get_adc[_mu]() docstring for clarity
...
This hopefully suggests a bit better that the value is the last one
fetched by the servo (i.e. needs the servo active to update), rather
than somehow requesting a new sample to be taken.
2019-07-30 12:22:08 +01:00
b8870997d0
doc: clarify TTL direction control with buffered cards
2019-07-24 10:04:45 +08:00
David Nadlinger
280915d54f
coredevice/suservo: Adjust T_CYCLE to match gateware
...
See GitHub #1338 .
2019-07-17 00:20:22 +01:00
f7e10759dc
suservo: note requirement to stop servo when accessing state
...
As already mentioned in the gateware.
One alternative would be to detect address collisions and
stall the read for one cycle.
Note that there will in general not be a consistent view of the servo
state unless the servo is stopped.
close #1337
2019-07-08 18:37:42 +02:00
David Nadlinger
8bf9640185
coredevice/suservo: Fix output IIR state width in docstring
2019-06-21 11:27:39 +02:00
David Nadlinger
34f48f57cc
coredevice/suservo: Fix {get,set}_y_mu() scaling
...
Previously, Channel.set_y(1) would set the output to -1 instead.
2019-06-21 11:27:39 +02:00
74e4b01201
urukul: document consequences of incorrect CPLD clock settings
2019-06-11 11:12:12 +08:00
adf3df2bb5
suservo coredevice driver: mask ftw to avoid erroneous sign extension
2019-06-03 21:40:04 +02:00
David Nadlinger
fc95183e04
coredevice: Fix host-side serialization of (nested) lists
...
Test case to follow.
2019-03-31 17:10:27 +01:00
d07c6fcfea
ad9910: handle unprogrammed EEPROM and numpy corner cases
2019-03-22 14:28:47 +08:00
04e0c23e78
ad9910: support reading synchronization values from EEPROM
2019-03-13 15:34:47 +08:00
964a349a19
add Kasli I2C driver
2019-03-13 15:33:50 +08:00
227c729f56
fix permissions
2019-03-11 20:43:28 +08:00
aee8965897
ad9910: add ram conversion tooling and unittests
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-02-21 15:59:52 +00:00
b57cad77ad
ad9910: make ram read work for short segments
...
also cleanup and style
Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-02-21 14:47:58 +00:00
hartytp
0ebff04ad7
SUServo: apply bit masks to servo memory writes to prevent overflows
...
Signed-off-by: TPH <thomas.harty@physics.ox.ac.uk>
2019-02-07 17:04:11 +01:00
hartytp
f6142816b8
Revert "SUServo: remove references to non-existent a0 parameter" ( #1270 )
...
This reverts commit f3aab2b891
2019-02-07 15:57:43 +00:00
hartytp
fe63c9b366
SUServo: remove references to non-existent a0 parameter ( #1268 )
...
Signed-off-by: Thomas Harty <thomas.harty@physics.ox.ac.uk>
2019-02-07 15:29:32 +00:00
hartytp
df6c1fca2c
SUServo: flake8 [NFC] ( #1267 )
...
Signed-off-by: Thomas Harty <thomas.harty@physics.ox.ac.uk>
2019-02-07 15:13:44 +00:00
8c5a502591
ad53xx: ignore F3 (reserved)
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-01-24 15:50:46 +01:00
330c5610e9
ad9912: fix imports
2019-01-23 17:59:08 +08:00
b692981c8e
ad9910: add note about red front panel led
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-01-22 12:49:42 +01:00
91e375ce6a
ad9910: don't reset the input divide-by-two
...
suspected of causing weird PLL lock timout errors
https://freenode.irclog.whitequark.org/m-labs/2019-01-22#1548148750-1548143221 ;
Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-01-22 09:37:20 +00:00
81ff3d4b29
ad9912: add some slack after init
2019-01-21 17:10:58 +00:00
84f7d006e8
ad9910: add precision about tune_io_update_delay/tune_sync_delay order
2019-01-21 19:40:55 +08:00
30051133b7
urukul: fix typos
2019-01-21 19:40:55 +08:00
40187d1957
ad9910: support configurable refclk divider and pll bypass
...
for #1248
* also always keep refclk input divider (by two) reset
2019-01-18 12:23:53 +00:00
385916a9a4
ad9912: support configurable clk_div
2019-01-18 12:16:08 +00:00
2bea5e3d58
urukul: support configurable refclk divider
...
for #1248
2019-01-18 12:09:32 +00:00
David Nadlinger
a565f77538
Add gateware input event counter
2019-01-15 10:55:07 +00:00
David Nadlinger
6c52359e59
coredevice: Add _mu suffix to AD991x ref_time arguments
...
GitHub: Fixes #1243 .
2019-01-12 17:34:35 +00:00
whitequark
49682d0159
Improve Python 3.7 compatibility.
...
async is now a full (non-contextual) keyword.
There are two more instances:
- artiq/frontend/artiq_client.py
- artiq/devices/thorlabs_tcube/driver.py
It is not immediately clear how to fix those, so they are left for
later work.
2019-01-12 13:17:59 +00:00
David Nadlinger
48fc175a6b
coredevice.ttl: More imperative mood in docstrings [nfc]
...
This follows Python conventions (PEP257) and unifies the style with
other comments.
2019-01-12 12:01:55 +00:00
David Nadlinger
3e84ec2bf1
coredevice.ad9910: Fix phase tracking ref_time passing
...
This is difficult to test without hardware mocks or some
form of phase readback, but the symptom was that e.g.
`self.dds.set(…, ref_time=now_mu() - 1)` would fail
periodically, that is, whenever bit 32 of the timestamp
would be set (which would be turned into the sign bit).
This is a fairly sinister issue, and is probably a compiler
bug of some sort (either accepts-invalid or wrong type inference).
2019-01-12 00:47:38 +00:00
101671fbbf
core_analyzer: support uniform VCD time intervals
...
close #1236
Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-01-10 19:35:09 +01:00
19748fe495
ad9910: fix RTIO fine timestamp nudging
...
Previously the TSC was truncated to an even coarse RTIO periods before doing
the setting SPI xfer. Afterwards the the IO update pulse would introduce
at least one but less than two RTIO cycles. Ultimately the RTIO TSC was
truncated again to even. If the SPI xfer takes an odd number of RTIO
periods, then a subsequent xfer would collide.
close #1229
Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-01-09 17:22:57 +00:00
b25ab1fc88
ad9910: add more slack in tune_sync_delay
...
close #1235
Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-01-09 16:07:31 +00:00
Drew
40370c4d45
Docs: fix build warnings ( #1234 )
...
* ad9910: finish CONT_RECIRCULATE -> CONT_RAMPUP
Found while building docs. Forgot to refactor strings.
Signed-off-by: Drew Risinger <drewrisinger@users.noreply.github.com>
* spi2: reformat update_xfer_duration_mu docstring
update_xfer_duration_mu docstring threw warning while building docs,
didn't use consistent indent in warning.
Signed-off-by: Drew Risinger <drewrisinger@users.noreply.github.com>
2019-01-09 11:39:23 +08:00
David Nadlinger
4fb434674d
coredevice: Fix ad9910 __all__ exports
2019-01-08 18:55:26 +00:00
David Nadlinger
cadde970e1
urukul: Expand CPLD sync_sel explanation [nfc]
2019-01-08 02:37:58 +00:00
David Nadlinger
7bcdeb825b
ad9910: Add inverse FTW/ASF conversions
2019-01-08 02:18:14 +00:00
David Nadlinger
4d793d7149
ad9910: Truncate phase word to 16 bits
...
This avoids overflowing into the asf portion of the register.
2019-01-08 02:18:14 +00:00
a7d4d3bda9
ad9910: CONT_RECIRCULATE -> CONT_RAMPUP
2018-12-17 13:25:00 +00:00
35bdf26f01
Merge branch 'ad9910-ram'
2018-12-17 21:16:44 +08:00
David Nadlinger
e608d6ffd3
coredevice, firmware: Add rtio_input_timestamped_data
...
Integration tests to follow as part of an RTIO counter phy that
makes use of this.
2018-12-15 00:35:04 +00:00
79eadb9465
ad9910: add RAM mode methods
...
* also refactor the CFR1 access into a method
c.f. #1154
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-12-11 14:54:16 +00:00
efd400b02c
ad9910: style [nfc]
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-12-11 11:36:25 +01:00
d90eb3ae88
ad9910: add read64()
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-12-07 21:27:00 +00:00
baf88050fd
urukul: expand attenuator HITL unittests
...
* read back with cleared backing state
* individual channel settings
* check backing state
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-12-07 21:06:12 +00:00
dce4f036db
grabber: work around windows numpy int peculiarity (same as a81c12de9)
2018-11-30 18:41:14 +08:00
450a035f9e
suservo: move overflowing RTIO address bits into data
2018-11-26 06:54:20 +08:00
b32e89444c
Merge branch 'master' into new
2018-11-26 01:02:19 +08:00
a81c12de94
urukul: work around windows numpy int peculiarity
...
"OverflowError: Python int too large to convert to C long" otherwise
opticlock#74
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-25 16:56:45 +01:00
8f9858be4c
ad9914: remove automatic continuous phase compensation (like Urukul)
2018-11-19 22:00:20 +08:00
53e79f553f
Merge branch 'master' into new
2018-11-19 11:54:50 +08:00
a3e0b1c5b4
ad9914,spi2: add warnings about driver state and DMA. Closes #1113
2018-11-17 22:10:20 +08:00
69e699c7bd
ttl: compensate for SED latency in input gating
...
Closes #1137
2018-11-17 22:10:20 +08:00
3ad68f65c5
urukul: make get_att_mu() not alter state
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-16 14:56:26 +00:00
d1eee7c0ea
ad9910: ensure sync is driven when required
...
close #1194
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-16 13:21:01 +00:00
1b841805f6
Merge branch 'master' into new
2018-11-16 15:20:32 +08:00
c3178c2cab
ad9910: profile support
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-14 08:30:28 +01:00
d0cadfeb4b
ad9910: more idiomatic register names
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-14 07:55:01 +01:00
a52d1be140
urukul: expose PROFILE setting
...
* add documentation
* add unittest
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-14 07:43:56 +01:00
a4997c56cf
ad9910: simplify edge detection logic
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-09 18:54:34 +00:00
14b6b63916
ad9910: rewire io_delay tuning
...
This now reliably locates the SYNC_CLK-IO_UPDATE edge by doing two
scans at different delays between start and stop IO_UPDATE.
It also works well when one delay is very close to the edge.
And it correctly identifies which (start or stop) pulse hit or crossed
the SYNC_CLK edge.
for #1143
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-09 18:38:27 +00:00
38c6878d49
urukul: mention min/max attenuation
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-09 13:32:05 +01:00
e565ca6b82
urukul: slow down att write to datasheet limit
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-09 13:23:06 +01:00
998be50f07
urukul: handle MSB in att_reg
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-09 13:21:14 +01:00
c990b5e4f1
Merge remote-tracking branch 'origin/master' into new
2018-11-08 20:21:56 +08:00
0bee43aa58
sawg: use new rtio_output() API
2018-11-08 20:16:30 +08:00
bec25cbaa0
suservo: use new rtio_output() API
2018-11-08 20:13:14 +08:00
e8d58b35b4
spi2: use new rtio_output() API
2018-11-08 20:12:30 +08:00
d18546550e
grabber: use new rtio_output() API
2018-11-08 19:15:50 +08:00
2549e623c1
ad9914: use new rtio_output() API
2018-11-08 19:15:44 +08:00
8caea0e6d3
gateware,runtime: optimize RTIO kernel interface further
...
* now pinning (TODO: atomicity)
* for inputs, merge request and timeout registers
2018-11-08 18:29:24 +08:00
fae95e73ad
ttl: use optimized rtio_output API
2018-11-07 23:41:43 +08:00
3d0c3cc1cf
gateware,runtime: optimize RTIO output interface
...
* reduce address to 8 bits
* merge core, channel and address into 32-bit pre-computable "target"
* merge we register into data register
2018-11-07 23:39:58 +08:00
e6efe830c4
ad9910: rewire sync delay tuning
...
* search from wide window end
* decouple margins and minimum window size
* add note about kasli jitter
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-07 14:52:03 +00:00
ad0254c17b
Merge branch 'switching125' into new
2018-11-07 22:03:18 +08:00
6c00ab57c0
test_ad9910: relax SYNC window
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-06 19:31:38 +01:00
172633c7da
test_ad9910: default to a useful seed
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-06 17:35:57 +01:00
0b2661a34d
ad9910: robustify SYNC window finding
...
don't integrate too long, find the window tip fast and early
a couple 100 SYNC pulses are sufficient
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-06 12:41:21 +00:00
31f68ddf6c
Merge branch 'urukul-sync'
...
* urukul-sync: (29 commits)
urukul: flake8 [nfc]
ad9910: flake8 [nfc]
urukul/ad9910 test: remove unused import
test_urukul: relax speed
urukul,ad9910: print speed metrics
kasli: add PTB2 (external clock and SYNC)
kasli: add sync to LUH, HUB, Opticlock
kasli_tester: urukul0 mmcx clock defunct
test_ad9910: relax ifc mode read
tests: add Urukul-AD9910 HITL unittests including SYNC
ad9910: add init bit explanation
test: add Urukul CPLD HITL tests
ad9910: fiducial timestamp for tracking phase mode
ad9910: add phase modes
ad9910: fix pll timeout loop
tester: add urukul sync
ptb: back out urukul-sync
ad9910: add IO_UPDATE alignment and tuning
urukul: set up sync_in generator
ad9910: add io_update alignment measurement
...
close #1143
2018-11-05 19:54:30 +01:00
6fb18270a2
urukul: flake8 [nfc]
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:45:24 +01:00
832690af9a
ad9910: flake8 [nfc]
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:44:51 +01:00
9fb850ae75
ad9910: add init bit explanation
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:37:02 +01:00
bc04da15c5
test: add Urukul CPLD HITL tests
...
for #1143
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:37:00 +01:00
141cc7d99f
ad9910: fiducial timestamp for tracking phase mode
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:58 +01:00
2f6d3f79ff
ad9910: add phase modes
...
* simplified and cross-referenced the explanation of the different
phase modes.
* semantically and functionally merged absolute and tracking/coherent
phase modes.
* simplified numerics to calculate phase correction
* added warning about possible inconsistency with DMA and default
phase mode
* restricted __all__ imports
* moved continuous/relative phase offset tracking from an instance
variable to a "handle" returned by set()/set_mu() in order to avoid
state inconsistency with DMA (#1113 #1115 )
for #1143
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:55 +01:00
d3ad2b7633
ad9910: fix pll timeout loop
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:53 +01:00
06139c0f4d
ad9910: add IO_UPDATE alignment and tuning
...
for #1143
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:48 +01:00
1066430fa8
urukul: set up sync_in generator
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:46 +01:00
4bbd833cfe
ad9910: add io_update alignment measurement
...
for #1143
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:44 +01:00
7b92282012
ad9910: add docs for sync tuning, refactor
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:42 +01:00
8a47a6b2fb
ad9910: disable sync_clk output
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:40 +01:00
65e2ebf960
ad9910: add sync delay control, auto tuning
...
* expose multi device sync functionality
* sync delay configuration interface
* auto-tuning of sync delay from device_db seed
for #1143
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:37 +01:00
8dbf5f87fd
ad9910: simplify io_update pulsing on init, set_mu
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:35 +01:00
0b3b07a7da
ad9910: add power down method
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:34 +01:00
0433e8f4fe
urukul: add sync_in generator
...
for #1143
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:30 +01:00
f62c1ff0bb
TTLClockGen: expose acc_width
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:27 +01:00
David Nadlinger
f79b9d9e1e
ttl: Expand input gate/count API docstrings
2018-11-03 20:33:19 +08:00
David Nadlinger
5d2e3f975f
coredevice: Add get_rtio_counter_mu() docstring [nfc]
2018-11-03 20:33:19 +08:00
David Nadlinger
d6fcc0529f
coredevice: Imperative mood in docstrings [nfc]
...
This follows Python conventions (PEP257) and unifies the style with
other comments.
2018-11-03 20:33:19 +08:00
David Nadlinger
cbdef0225c
ttl: Add target RTIO time argument to timestamp/count functions
...
Software-based tracking of timestamps is problematic (e.g. when
using DMA, see GitHub #1113 ).
2018-11-03 20:33:19 +08:00
David Nadlinger
2a0e1dabfb
ttl: Remove unused attribute [nfc]
2018-11-03 20:33:19 +08:00
David Nadlinger
17a5fb2dce
ttl: Remove error-prone sync() calls
...
These methods are problematic, as with DMA in the picture, the
timestamp member variables did not necessarily reflect the last
submitted event timestamp (see GitHub #1113 ).
sync() is only very rarely used in typical experimental code, so
the methods are removed without a transition period.
Core.wait_until() can be used to busy-wait for a specified RTIO
timestamp value on the core device CPU instead.
2018-11-03 20:33:19 +08:00
David Nadlinger
11e8c9d5f7
coredevice: Add Core.wait_until_mu()
...
(This supersedes TTLOut.sync(), see see GitHub #1113.)
2018-11-03 20:33:19 +08:00
David Nadlinger
cbfbe24d7a
ttl: Remove broken TTLClockGen.sync
...
The code currently doesn't compile because of a typo in the timestamp
field name. However, tracking event timestamps in software is
problematic anyway (e.g. with DMA, see GitHub #1113 ), so just remove
`sync()` altogether.
2018-11-03 20:33:19 +08:00
89a961fb00
urukul, ad9912, ad9910: expose CFG RF switch better
...
* conincident setting of multiple switches
* per channel setting
2018-10-24 13:04:46 +02:00
661dd00c4c
ad9912: phase offset is 14 bit LSB aligned
...
c.f. sinara-hw/Urukul#15
2018-10-11 15:16:08 +02:00
hartytp
08074d5275
Urukul: add support for hardware v1.3 clocking options
2018-10-10 09:26:35 +02:00
hartytp
1a1b454ed9
Urukul: flake8 (NFC)
2018-10-08 10:09:49 +01:00
hartytp
9a509e5070
Zotino: increase delay after register read in init method to avoid underflows
2018-10-06 21:45:17 +08:00
969a305c5a
Merge branch 'master' into switching125
2018-10-04 10:08:42 +08:00
c71e442929
documentation improvements
...
Based on PR #1101 by @drewrisinger
2018-09-26 12:12:37 +08:00
c8cd830118
drtio: implement get_rtio_destination_status for kernels
2018-09-15 19:11:22 +08:00
d38755feff
drtio: implement destination state checks on operations
2018-09-15 15:55:45 +08:00
95432a4ac1
drtio: remove old debugging features
2018-09-12 13:01:27 +08:00
whitequark
a74958f01f
ksupport: raise RuntimeError on reraise with no inflight exception.
...
Fixes #1123 .
2018-08-07 05:53:13 +00:00
6fc8439399
tweak moninj to allow old dashboard with new firmware
2018-08-02 19:34:14 +08:00
47740c8930
share moninj injection state between dashboards
...
Previously if one dashboard overrode a channel this was not visible on
any other dashboard - the channel appeared to operate normally.
2018-08-02 19:34:14 +08:00
7d6a1b528d
ad9912: add ftw_to_frequency
2018-08-02 11:19:12 +00:00
e518a1f1d0
ad53xx: also increase slack after control readback
2018-08-02 11:19:12 +00:00
David Nadlinger
08ee91beb2
ad9910: Clarify chip_select range [nfc]
...
`assert 3 <= chip_select <= 7` is rather opaque without looking
at the CPLD source code otherwise.
2018-07-30 11:08:17 +01:00
David Nadlinger
6b89106578
ad53xx: Avoid sporadic RTIOUnderflow in init()
...
I observed sporadic RTIO underflows on Kasli before, by ~2.5 µs,
so 5 µs extra slack should be plenty. No underflows since.
2018-07-28 23:45:48 +01:00
fb96c1140e
grabber: add coredevice driver
2018-07-24 18:06:44 +08:00
cab0ba408d
fmcdio_vhdci_eem: cleanup and document
2018-07-20 09:57:03 +08:00
8dfcd463aa
fmcdio_vhdci_eem: naming consistency
2018-07-19 15:46:04 +08:00
fe93a454d6
fmcdio_vhdci_eem: fix direction shift register permutation and polarity
2018-07-19 15:16:21 +08:00
8b9a8be12a
fmcdio_vhdci_eem: add dirctl word computation functions
2018-07-17 23:27:29 +08:00
d4d12e264d
fmcdio_vhdci_eem: refactor
...
This allows access to the pin allocation from kernels, which becomes useful
to configure the direction shift register.
2018-07-17 20:13:59 +08:00
b27fa8964b
add variant in identifier string
...
Also add without-sawg suffixes on Sayma.
Closes #1060
Closes #1059
2018-07-15 17:21:17 +08:00
whitequark
12fde6d34b
artiq_coremgmt: fix typo.
...
Fixes #1056 .
2018-06-23 00:36:59 +00:00
21a48711ec
i2c: refactor common operations
2018-06-18 09:34:09 +00:00
f9910ab242
i2c: support selecting multiple or no channels
...
closes #1054
2018-06-15 19:36:37 +02:00
735e4e8561
pcu: spelling
2018-06-08 14:39:22 +00:00
38971d130a
comm_analyzer: fix data without any spi reads
...
closes #1050
2018-06-06 12:21:42 +02:00
5de2d06568
ad53xx/zotino: do not clear power down on overtemp
2018-06-01 13:17:13 +00:00
2c344686d9
ad53xx/zotino: enable overtemp shutdown and readback control
2018-06-01 13:06:52 +00:00
87d3ac9d25
suservo: swap transfer function parametrization
...
The integrator is now parametrized through its gain and not the PI
corner frequency. The integrator gain limit is given in absolute gain
units and not relative to the proportional gain.
close #1033
2018-06-01 09:38:18 +00:00
e408241233
sawg: work around compiler not accepting delay_mu(int32)
2018-06-01 15:42:37 +08:00
f5d55c6902
sawg: add 1 coarse RTIO cycle between spline resets
...
This keeps all events in the same SED lane and limits the number of SED lanes required.
Closes #1038
2018-06-01 15:15:24 +08:00
22506e849f
suservo: clarify timings
...
close #1027
2018-06-01 06:35:38 +00:00
a42f774440
suservo: document offset range limits
...
close #1034
2018-05-31 16:55:44 +00:00
36dcea3edf
suservo: refactor y_mu_to_full_scale as portable
...
close #1032
2018-05-31 16:44:14 +00:00
e136709cac
suservo: document gain state
...
close #1030
2018-05-31 16:36:53 +00:00
5dbdc5650c
suservo: document set_config and get_status more
...
close #1028
2018-05-31 16:32:05 +00:00
e1b0fcc24e
suservo: add documentation on settings and setup
...
close #1015
2018-05-31 16:21:09 +00:00
4e863b32a1
coredevice: configurable initial backing state
...
Several core device drivers maintain a copy of some device state.
Since this copy is not transferred between experiments this backing state
can be different from device state when a new experiment is started.
This commit adds support for injecting initial backing state into
experiments via the device database and sets initial backing state where
known.
ad53xx (zotino): spi2 xfer_duration
novogorny: pgia gains
sampler: pgia gains, spi2 pgia and adc xfer_duration
suservo: pgia gains, spi2 pgia xfer_duration
urukul: cpld cfg (partial: rf_sw), attenuator register
spi2: div/length for xfer_duration
close #1003
2018-05-21 18:55:06 +02:00
8513f0b0d4
minor cleanup
2018-05-21 15:35:00 +08:00
b10d3ee4b4
make RTIO clock switch optional and simplify
...
Kasli no longer has an internal RTIO clock.
Switching clocks dynamically is no longer supported.
2018-05-18 17:41:34 +08:00
bfff755295
urukul: do IO_RST also when blind
2018-05-17 14:48:49 +00:00
whitequark
31c6c79204
firmware: implement an edge profiler.
...
It doesn't work extremely well, and the results can be somewhat
confusing, and it needs a libunwind patch, but it's the best I could
do and it seems still useful.
2018-05-16 21:53:53 +00:00
99f7672c79
ad53xx: tweak spi readback
2018-05-16 19:08:27 +02:00
whitequark
4d06c1d84b
coredevice.CommKernel: modernize. NFC.
2018-05-16 14:40:14 +00:00
whitequark
ca93b94aea
firmware: move config requests to management protocol.
...
They were only in session protocol because of historical reasons.
2018-05-16 14:32:49 +00:00
whitequark
a39f8d6634
artiq_devtool: use CommMgmt instead of shelling out to artiq_coremgmt.
...
(Which no longer exists.)
This also fixes `artiq_devtool hotswap` to work without
an `artiq_devtool connect` running in background.
2018-05-16 14:08:32 +00:00
whitequark
d446a3293e
frontend: merge core{config,log,boot,debug,profile} into coremgmt.
2018-05-16 14:08:32 +00:00
a100c73dfe
suservo: support pure-I
2018-05-14 18:48:27 +00:00
e121a81f21
ad9914: fix frequency_to_xftw and xftw_to_frequency
2018-05-14 23:49:00 +08:00
80df86f700
ad9914: set_mu_x -> set_x_mu
2018-05-14 23:49:00 +08:00
4ddb29fa02
suservo: document class arguments
2018-05-14 15:22:47 +02:00
504d37b66b
suservo: add SI units functions and document
...
m-labs/artiq#788
2018-05-14 12:26:49 +00:00
4993ceec35
sampler: unroll conversion for speed
2018-05-14 12:26:49 +00:00
ba1d137d19
ad9914: fix FTW write in regular resolution mode
2018-05-14 18:47:23 +08:00
b04c7abde8
ad9914: fix kernel_invariants
2018-05-14 14:02:11 +08:00
56a18682a7
ad9914: minor fixes
2018-05-14 10:37:50 +08:00
194d6462ee
ad9914: fix set_mu
2018-05-14 00:19:09 +08:00
hartytp
00cb31b804
sampler: remove v_ref parameter ( #988 )
2018-05-13 18:00:57 +02:00
3027951dd8
integrate new AD9914 driver
...
moninj, analyzer, docs, examples, tests.
2018-05-13 23:29:35 +08:00
663d8e66ba
ad9914: optimize extended-resolution mode
2018-05-13 23:01:06 +08:00
c8d91b297d
coredevice: add new ad9914 driver
2018-05-13 22:30:33 +08:00
f055bf88f6
suservo: add clip flags ( #992 )
2018-05-09 07:16:15 +00:00
whitequark
b1d349cc1b
firmware: implement a sampling profiler.
...
Does not yet support constructing call graphs.
2018-05-05 00:44:40 +00:00
ae80bab180
urukul: reg based io-update is a kernel
2018-04-27 16:42:09 +00:00
5f00326c65
suservo: coeff mem write port READ_FIRST
2018-04-27 15:43:32 +00:00
73fa572275
suservo: documentation, small API changes
2018-04-27 16:53:22 +02:00
307cd07b9d
suservo: lots of gateware/ runtime changes
...
tested/validated:
* servo enable/disable
* dds interface, timing, io_update, mask_nu
* channel control (en_out, en_iir, profile)
* profile configuration (coefficients, delays, offsets, channel)
* adc timings and waveforms measured
* asf state readback
* adc readback
individual changes below:
suservo: correct rtio readback
suservo: example, device_db [wip]
suservo: change rtio channel layout
suservo: mem ports in rio domain
suservo: sck clocked from rio_phy
suservo: cleanup, straighten out timing
suservo: dds cs polarity
suservo: simplify pipeline
suservo: drop unused eem names
suservo: decouple adc SR from IIR
suservo: expand coredevice layer
suservo: start the correct stage
suservo: actually load ctrl
suservo: refactor/tweak adc timing
suservo: implement cpld and dds init
2018-04-27 13:50:26 +02:00
01f762a8f5
urukul/ad9910: support blind init
...
urukul: always set io_update attribute
to silence compiler warning w.r.t. kernel_invariants
2018-04-27 13:48:40 +02:00
edbc7763e0
urukul: allow no io_update_device
2018-04-25 17:32:36 +00:00
c47d3ec8c8
zotino: use None as default for ldac and clr
...
This is also what AD53xx does.
2018-04-22 15:03:01 +08:00
whitequark
3b054855ec
firmware: add allocator debug feature, invoked by artiq_coredebug frontend.
2018-04-21 19:39:46 +00:00
5ca59467fd
ad53xx: make LDAC and CLR optional
2018-03-26 22:45:01 +08:00
a8f0ee1c86
ad53xx: refactor offset_to_mu(), fix docs
2018-03-24 15:45:42 +01:00
b0c8097025
ad53xx: remove channel index AND
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It's incorrect since it doesn't respect the number of channels
of any of those chips (none has 64 channels).
2018-03-24 15:39:06 +01:00
77bcc2c78f
zotino: style, use attributes to set SPI config
2018-03-24 15:37:34 +01:00
2cf414a480
ad53xx: move 8 bit shift out of ad53xx protocol funcs
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That's specific to the SPI bus, not to the ad53xx.
2018-03-24 15:15:56 +01:00
08326c5727
ad53xx: style [nfc]
2018-03-24 14:10:20 +01:00
hartytp
a992a672d9
coredevice/zotino: add ( #969 )
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* Replace ad5360 driver with a ad53xx driver, designed to have a nicer interface
Add Zotino driver and add to opticlock target for Kasli
Test Zotino on hw:
- Verify all timings on the hardware with a scope
- Verify that we can correctly set and read back all registers in a loop (checks for SI and driver issues)
- check we can set LEDs correctly
- check calibration routine + all si unit functions with a good DVM
- look at DAC transitions on a scope (while triggering of a TTL) on persist to check there are no LDAC glitches etc
To do: update examples and e.g. KC705 device db.
2018-03-24 13:41:18 +01:00
770b0a7b79
novogorny: conv -> cnv
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* parity with sampler
* also add novogorny device to opticlock
2018-03-21 18:38:42 +00:00
82c4f0eed4
sampler: fix channel gain retrieval
2018-03-21 14:22:13 +01:00
97918447a3
sampler: add coredevice driver
2018-03-21 12:21:53 +00:00
80903cead7
novogorny: streamline gain setting method, style [nfc]
2018-03-21 08:53:26 +00:00
9ad1fd8f25
urukul: add comment and doc about the AD9910 MASTER_RESET
2018-03-20 17:40:03 +01:00
f17c0abfe4
urukul: don't pulse DDS_RST on init
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closes m-labs/artiq#940
Apparently, if the DDS are reset, every other time they don't work
properly.
2018-03-20 16:10:26 +00:00
a185e8dc52
urukul: fix MASK_NU offset
2018-03-20 16:10:11 +00:00
hartytp
a27b5d88c2
Novogorny driver, remove unused imports ( #964 )
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* Novogorny driver, remove unused imports
* more unused imports
* oops, one final one!
2018-03-19 11:58:14 +01:00
f39b7b33e8
ad5360: whitespace [nfc]
2018-03-17 18:51:17 +01:00
ion
c1439bfd3b
Fix AD5360 after migration to SPI2
2018-03-17 11:37:11 +00:00
a04bd5a4fd
spi2: xfers take one more cycle until ~busy
2018-03-09 20:48:17 +01:00
37ec97eb28
ad9910/2: add sw invariant only when passed
2018-03-07 21:32:59 +01:00
f4dad87fd9
coredevice: add pcf8574a driver
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I2C IO expander with 8 quasi-bidirectional pins
2018-03-06 14:27:19 +01:00
432e61bbb4
drtio: add kernel API to check for link status. Closes #941
2018-03-05 00:23:55 +08:00
928d5dc9b3
drtio: raise RTIOLinkError if operation fails due to link lost ( #942 )
2018-03-04 01:02:53 +08:00
abfbadebb5
doc: DMA can also raise RTIOUnderflow
2018-03-03 13:14:34 +08:00
cc70578f1f
remove old spi RTIO Phy
2018-03-01 11:19:18 +01:00
a7720d05cd
firmware, sayma: port converter_spi to spi2
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* ksupport/nrt_bus
* port ad9154, hmc830, hmc7043
* port local_spi and drtio_spi
* port kernel_proto libdrtioaux, satman
* change sayma_rtm gateware over
* add spi2 NRTSPIMaster
* remove spi NRTSPIMaster
* change sayma device_db
* change HMC830 to open mode and explicitly sequence open mode
2018-03-01 11:19:18 +01:00
5046d6a529
ad9912/10: add a bit more slack to init()
2018-02-27 23:14:44 +01:00
b466a569bf
coredevice: export spi2
2018-02-24 09:49:31 +01:00
cff85ee13b
novogorny: simplify and fix coefficient
2018-02-23 10:09:44 +01:00
bc5e949bb4
novogorny: fix gain register length
2018-02-22 18:45:55 +00:00
1452cd7447
novogorny: add coredevice driver and test with Kasli
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m-labs/artiq#687
2018-02-22 17:19:51 +01:00
74517107f0
ad9912: add slack after prodid read
2018-02-22 17:19:51 +01:00
e8d4db1ccf
coreanalyzer: add spi2 support
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m-labs/artiq#926
2018-02-22 11:28:46 +01:00
f8e6b4f4e3
ad5360: port to spi2
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* kc705 nist_clock target gateware
* coredevice driver
* moninj code
* test/example/device_db
This is untested as we don't have a AD5360 board right now.
Will be tested with Zotino v1.1
m-labs/artiq#926
2018-02-22 10:25:46 +01:00
898bad5abc
spi2: fixes
2018-02-21 19:41:05 +01:00
