M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity
7,915 Commits 13 Branches 35 Tags 26 MiB
Commit Graph

7915 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 4834966798 flake: add jsonschema to dev environment 2021-09-13 07:39:15 +08:00
Sebastien Bourdeauducq 7209e6f279 flake: add cargo-xbuild to dev environment 2021-09-13 07:20:36 +08:00
Sebastien Bourdeauducq ffb1e3ec2d wavesynth: np.int is deprecated 2021-09-13 07:02:35 +08:00
Sebastien Bourdeauducq 2d79d824f9 firmware: remove minor or1k leftovers 2021-09-12 20:03:37 +08:00
Sebastien Bourdeauducq 1a0c4219ec doc: mor1kx -> VexRiscv 2021-09-12 19:27:00 +08:00
Sebastien Bourdeauducq 2e5c32878f flake: add other KC705 NIST builds 2021-09-10 17:19:32 +08:00
occheung a573dcf3f9 board_misoc/build: use rv32 as target arg 
The original rv64 argument was only to match the misoc counterpart.
 2021-09-10 14:11:23 +08:00
occheung 448974fe11 runtime/main: cleanup 2021-09-10 13:59:53 +08:00
occheung b091d8cb66 kernel: flush cache before mod_init 
This could be necessary as redirecting instructions from D$ directly to I$ as it seems.
Related: https://github.com/SpinalHDL/VexRiscv/issues/137
 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq d50e24acb1 update dependencies 2021-09-10 13:25:12 +08:00
occheung 5394d04669 test_spi: add delay 2021-09-10 13:25:12 +08:00
occheung b8ed5a0d91 alloc: fix alignment for riscv32 arch 2021-09-10 13:25:12 +08:00
occheung 2213e7ffac ksupp/rtio/exception: fix timestamp 2021-09-10 13:25:12 +08:00
occheung 09ffd9de1e dma: fix timestamp fetch 2021-09-10 13:25:12 +08:00
occheung 051a14abf2 rtio/dma: fix endianness 2021-09-10 13:25:12 +08:00
occheung c6ba0f3cf4 ksupport: fix dma cslice (ffi) 2021-09-10 13:25:12 +08:00
occheung c812a837ab runtime: enlarge stack size 2021-09-10 13:25:12 +08:00
occheung a596db404d satman: fix cargo xbuild sysroot 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq eff7ae5aff flake: make llvm-strip in HITL test 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq c78fbe9bd2 flake: make bscanspi bitstreams available in HITL test 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq 17b9d2fc5a flake: add KC705 HITL test 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq 5e2664ae7e flake: add openocd 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq 64ce7e498b flake: make board package a Python package 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq 952acce65b flake: build board package on Hydra 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq 7ae4b2d9bb flake: update dependencies 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq ce0964e25f flake: fix cargo sha256 2021-09-10 13:25:12 +08:00
occheung 4fab267593 cargo: std dependency hack 2021-09-10 13:25:12 +08:00
occheung dcbd9f905c cargo: use cargo xbuild 2021-09-10 13:25:12 +08:00
occheung 9f6b3f6014 firmware: clarify target triple 
The lack of compressed instruction support can be inferred from the target triple, literally.
 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq 9697ec33eb flake: update dependencies 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq eee80c7697 flake: use improved Rust support in nixpkgs 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq b7efb2f633 flake: remove outdated comment 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq 9ee03bd438 flake: reenable lit test 2021-09-10 13:25:12 +08:00
occheung 4619a33db4 test: remove broken array return tests 
Removed test cases that do not respect lifetime/scope constraint.
See discussion in artiq-zynq repo: M-Labs/artiq-zynq#119
Referred to the patch from @dnadlinger. 5faa30a837
 2021-09-10 13:25:12 +08:00
occheung 5985f7efb5 syscall: lower nowrite to inaccessiblememonly 
In the origin implementation, the `nowrite` flag literally means not writing memory at all.
Due to the usage of flags on certain functions, it results in the same issues found in artiq-zynq after optimization passes. (M-Labs/artiq-zynq#119)
A fix wrote by @dnadlinger can resolve this issue. (c1e46cc7c8)
 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq 6db7280b09 flake: board package WIP 2021-09-10 13:25:12 +08:00
occheung d8ac429059 dyld: streamline lib.rs 
Only riscv32 is supported anyway, no need to have excessive architecture check.
 2021-09-10 13:25:12 +08:00
occheung 798774192d slave_fpga/bootloader: read in little endian 2021-09-10 13:25:12 +08:00
occheung eecd825d23 firmware: suppress warning 2021-09-10 13:25:12 +08:00
occheung 1da0554a49 pcr: purge 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq 035d15af9d flake: clean up vivado, add installer environment 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq 9addd08587 flake: fetch MiSoC submodules 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq 3e09e48152 flake: set up Vivado 2021-09-10 13:25:12 +08:00
occheung 5d0a8cf9ac llvm_ir_gen: fix indent 2021-09-10 13:25:12 +08:00
occheung 70507e1b72 Cargo.lock: update 2021-09-10 13:25:12 +08:00
occheung c113cd6bf5 libfringe: bump 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq 251cd4dcc6 flake: update dependencies 2021-09-10 13:25:12 +08:00
occheung 61b0170a12 firmware: purge or1k 2021-09-10 13:25:12 +08:00
occheung af263ffe1f ksupport: fix rpc, cache signature (FFI) 
The reason of the borrow stuff is explained in M-Labs/artiq-zynq#76 (artiq-zyna repo).
As for `cache_get()`, compiler will perform stack allocation to pre-allocate the returned structure, and pass to cache_get alongside the `key`.
However, ksupport fails to recognize the passed memory, so it will always assume the passed memory as the key.
 2021-09-10 13:25:12 +08:00
occheung a833974b50 analyzer: fix endianness 2021-09-10 13:25:12 +08:00