f0b0b1bac7
support for multiple DDS buses (untested)
2016-03-09 17:12:50 +08:00
9d1903a4e2
coredevice/i2c,ttl,spi: consistent device get
2016-03-09 13:01:34 +08:00
71105fd0d7
rtio: collision_error -> collision
2016-03-08 15:38:35 +08:00
c73b080019
doc/PCA9548: clarify channel selection
2016-03-07 00:17:45 +08:00
2770d9c729
doc: I2C/QC2
2016-03-05 19:02:03 +08:00
683716017b
test: I2C/PCA9548 unittest
2016-03-05 19:01:35 +08:00
f2b4b975a3
ad5360: add documentation and an example
2016-03-04 23:36:17 +01:00
18ccac717b
ad5360: t16 is a max
2016-03-04 19:46:18 +01:00
eb2ec40b3a
ad5360: un-factor write_channels
2016-03-04 19:01:29 +01:00
725943fee2
ad5360: add busy and update timings
2016-03-04 18:53:05 +01:00
e834a88340
ad5360: style
2016-03-04 18:15:35 +01:00
710717ca9b
ad5360: add batched zero-length multi-channel set()
2016-03-04 18:14:31 +01:00
4ae3ca5f23
spi/ad5360: refactor, small fixes
2016-03-04 18:14:31 +01:00
200cddc346
coredevice/i2c: fix exception message
2016-03-05 00:51:13 +08:00
70f0a7447f
coredevice/PCA9548: fix I2C address
2016-03-05 00:47:24 +08:00
df71b82037
coredevice/i2c: fix imports
2016-03-05 00:43:13 +08:00
2f1a2782d2
coredevice: add I2C, PCA9548, TCA6424A drivers
2016-03-05 00:17:41 +08:00
ff4a46c278
runtime/i2c: make syscalls more ARTIQ-Python-friendly
2016-03-05 00:16:23 +08:00
3364827744
ttl/TTLClockGen: fix FTW computation with ref_multiplier != 1
2016-03-04 16:59:59 +08:00
4352d15016
coredevice/core: add ref_multiplier and coarse_ref_period attributes
2016-03-04 16:59:35 +08:00
whitequark
6e44c5424d
coredevice.ttl: add missed int64 conversion.
2016-03-04 08:37:43 +00:00
669fbaa4f1
ad53xx->ad5360 and refactor
2016-03-04 00:00:25 +01:00
dc6d116824
spi: have write() delay by transfer duration
2016-03-03 21:57:27 +01:00
9969cd85de
ad53xx: ldac may be none
2016-03-02 15:50:02 +01:00
1e4bccae20
ad53xx: add
2016-03-02 00:12:01 +01:00
162ecdd574
spi: cleanup, add frequency_to_div()
2016-03-02 00:11:17 +01:00
d973eb879f
coredevice.spi: docstring fix
2016-03-01 22:42:00 +01:00
f754d2c117
Merge branch 'spimaster'
...
* spimaster: (52 commits)
runtime/rtio: rtio_process_exceptional_status() has only one user
coredevice.spi, doc/manual: add spi
kc705: move ttl channels together again, update doc
runtime: rt2wb_input -> rtio_input_data
examples/tdr: adapt to compiler changes
bridge: really fix O/OE
runtime: define constants for ttl addresses
coredevice.ttl: fix sensitivity
bridge: fix ttl o/oe addresses
runtime: refactor ttl*()
rtio: rm rtio_write_and_process_status
coredevice.spi: unused import
rt2wb, exceptions: remove RTIOTimeout
gateware.spi: delay only writes to data register, update doc
nist_clock: disable spi1/2
runtime/rt2wb: use input/output terminology and add (async) input
examples: update device_db for nist_clock spi
gateware.spi: rework wb bus sequence
nist_clock: rename spi*.ce to spi*.cs_n
nist_clock: add SPIMasters to spi buses
...
2016-03-01 22:08:08 +01:00
0456169558
coredevice.spi, doc/manual: add spi
2016-03-01 21:29:09 +01:00
f30dc4b39e
runtime: rt2wb_input -> rtio_input_data
2016-03-01 19:22:42 +01:00
3aebbbdb61
coredevice.ttl: fix sensitivity
2016-03-01 18:22:03 +01:00
8adef12781
runtime: refactor ttl*()
...
* remove rt2wb_output
* remove ttl_*() ttl.c ttl.h
* use rtio_output() and rtio_input_timestamp()
* adapt coredevice/compiler layer
* adapt bridge to not artiq_raise_from_c()
2016-03-01 16:36:59 +01:00
29776fae3f
coredevice.spi: unused import
2016-03-01 15:38:40 +01:00
324660ab40
rt2wb, exceptions: remove RTIOTimeout
...
Assume that rt2wb transactions either collide and are then
reported (https://github.com/m-labs/artiq/issues/308 ) or that
they complete and the delay with which they complete does not matter.
If a transaction is ack'ed with a delay because the WB core's downstream
logic is busy, that may lead to a later collision with another WB
transaction.
2016-03-01 14:44:07 +01:00
c7d48a1765
coredevice/TTLOut: add dummy output function
2016-03-01 19:03:10 +08:00
7d7a710a56
runtime/rt2wb: use input/output terminology and add (async) input
2016-03-01 00:35:56 +01:00
7ab7f7d75d
Merge branch 'master' into spimaster
...
* master:
artiq_flash: use term 'gateware'
targets/kc705-nist_clock: add clock generator on LA32 for testing purposes
doc: insist that output() must be called on TTLInOut. Closes #297
doc: update install instructions
coredevice: do not give up on UTF-8 errors in log. Closes #300
use m-labs setup for defaults
fix indentation
2016-02-29 20:47:52 +01:00
6c899e6ba6
runtime/rtio: fix rtio_input_wait(), add RTIOTimeout
2016-02-29 19:49:15 +01:00
16537d347e
coredevice.spi: cleanup
2016-02-29 19:48:26 +01:00
e11366869d
coredevice/spi: clean up api
2016-02-29 17:54:42 +01:00
a1e1f2b387
doc: insist that output() must be called on TTLInOut. Closes #297
2016-03-01 00:28:40 +08:00
4467f91cbf
coredevice: do not give up on UTF-8 errors in log. Closes #300
2016-02-29 22:21:10 +08:00
c226aeb0d4
coredevice/spi: read_sync read bit
2016-02-29 14:55:29 +01:00
df7d15d1fe
runtime: refactor spi into rt2wb
2016-02-29 13:54:36 +01:00
8b2b278457
spi: add coredevice support
2016-02-29 00:44:48 +01:00
whitequark
cf41890255
Correctly display backtraces that contain inlined functions.
2016-02-24 17:44:19 +00:00
whitequark
950eaef08c
coredevice: re-export more exceptions.
2016-02-24 15:09:22 +00:00
whitequark
9db2be2b03
compiler: only use colors in diagnostics on POSIX ( fixes #272 ).
2016-02-22 11:27:45 +00:00
whitequark
a5977a5b62
Commit missing parts of 1465fe6f8.
2016-02-15 21:42:51 +00:00
68891493a3
analyzer: move common to artiq.protocols
...
migen was still pulled in through rtio.__init__.py
2016-01-29 20:26:48 -07:00
