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568 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 738d2c6bcb hmc7043: REFSYNCIN → RFSYNCIN 2018-08-11 12:07:17 +08:00
Robert Jördens f7678cc24a grabber: refactor state machine 2018-08-07 18:07:46 +02:00
Robert Jördens 6cd2432e30 grabber: log all resolution changes 
close #1120
 2018-08-07 16:21:21 +02:00
Robert Jördens 99a15ca0c6 grabber: rationalize derived traits 2018-08-07 16:21:21 +02:00
Sebastien Bourdeauducq 49f7a1610f sayma: use GTP_CLK1 only for all variants (#1080) 2018-08-07 20:53:14 +08:00
whitequark 7bd7b6592a rpc_proto: serialize keywords correctly. 
Fixes #1109.
 2018-08-07 06:47:09 +00:00
whitequark a74958f01f ksupport: raise RuntimeError on reraise with no inflight exception. 
Fixes #1123.
 2018-08-07 05:53:13 +00:00
Sebastien Bourdeauducq 2008d02f4d runtime: use different default IP and MAC for different kinds of boards 
This helps reduce conflicts when having many boards on a development network.
 2018-08-07 10:30:50 +08:00
Sebastien Bourdeauducq bbe36b94f7 ad9154: enable sync in init 2018-08-06 19:02:27 +08:00
Sebastien Bourdeauducq 7f0b2ff594 jesd204sync: work around HMC7043 poor behavior with combined delays 
The HMC7043 outputs poorly controlled signals when adjusting
two delays at once. This commit puts the DAC in one-shot SYSREF mode,
and only triggers synchronizations when SYSREF is stable.
 2018-08-06 17:43:17 +08:00
Sebastien Bourdeauducq f32f0126e2 Revert "ad9154: use continuous sync mode" 
The HMC7043 is not really glitchless.

This reverts commit bd968211de.
 2018-08-06 16:59:53 +08:00
Sebastien Bourdeauducq bd968211de ad9154: use continuous sync mode 2018-08-06 00:27:10 +08:00
Sebastien Bourdeauducq e83ee3a07a hmc7043: disable GTP_CLK1 when not in use 
Termination and biasing are not active at the FPGA when IBUFDS_GTE3 is
not instantiated, and driving a clock then leads to overvoltage.
 2018-08-03 10:03:52 +08:00
Chris Ballance 6fc8439399 tweak moninj to allow old dashboard with new firmware 2018-08-02 19:34:14 +08:00
Chris Ballance 47740c8930 share moninj injection state between dashboards 
Previously if one dashboard overrode a channel this was not visible on
any other dashboard - the channel appeared to operate normally.
 2018-08-02 19:34:14 +08:00
whitequark 5871d13da8 firmware: actually compact in config::compact(). 
Fixes #1116.
 2018-08-01 16:27:48 +00:00
Sebastien Bourdeauducq e4d48a78eb drtio: wait for remote to ack TSC synchronization 
Sayma takes a long time after TSC sync to align SYSREF, and this caused two issues:
1. Aux packets getting lost and causing error reports
2. DRTIO links reported up and kernels proceeding despite the DACs not being properly synced.
 2018-07-26 20:28:17 +08:00
Sebastien Bourdeauducq 83de8b2ba2 drtio: add ping timeout during link init 2018-07-26 20:27:53 +08:00
Sebastien Bourdeauducq 446f791180 firmware: simplify SYSREF DRTIO alignment 2018-07-26 19:37:59 +08:00
Sebastien Bourdeauducq f8c17528e7 satman: use new SYSREF code 2018-07-26 16:26:57 +08:00
Sebastien Bourdeauducq 32c95ac034 sayma: automated DAC SYSREF phase calibration 2018-07-26 16:23:55 +08:00
Sebastien Bourdeauducq dbcf2fe9b4 firmware: remove 'chip found' messages on Sayma 2018-07-26 16:07:37 +08:00
Sebastien Bourdeauducq d523d03f71 sayma: automated FPGA SYSREF phase offset calibration 2018-07-26 14:53:28 +08:00
Sebastien Bourdeauducq 0a9d3638ee config: add write_int 2018-07-26 14:49:32 +08:00
Sebastien Bourdeauducq 19c51c644e grabber: cleanup GRABBER_STATE 2018-07-24 19:08:51 +08:00
Sebastien Bourdeauducq e71cbe53a6 firmware: cleanup Cargo.lock 2018-07-18 10:37:43 +08:00
Sebastien Bourdeauducq 13984385a8 firmware: version → ident 2018-07-15 17:40:17 +08:00
Sebastien Bourdeauducq b27fa8964b add variant in identifier string 
Also add without-sawg suffixes on Sayma.

Closes #1060
Closes #1059
 2018-07-15 17:21:17 +08:00
Sebastien Bourdeauducq 46fb5adac3 grabber: fix frequency counter formula 2018-07-12 20:14:38 +08:00
Sebastien Bourdeauducq 82def6b535 grabber: add frequency counter 
Cameras are a bit obscure about what they output, this can help with troubleshooting.
 2018-07-12 17:05:18 +08:00
Sebastien Bourdeauducq 29c35ee553 hmc7043: fix dumb mistake in previous commit 2018-07-12 13:01:41 +08:00
Sebastien Bourdeauducq 8802b930de hmc7043: add delay after init 
Delay required at step 9 of the "Typical Programming Sequence" (page 24 of the datasheet)
 2018-07-12 12:37:12 +08:00
Sebastien Bourdeauducq c66f9483f8 hmc7043: wait after changing delays 
Allows for the SPI transaction to finish, and for the delay to stabilize.
 2018-07-12 12:33:53 +08:00
Sebastien Bourdeauducq 1c191a62bf sayma: tune SYSREF phases 2018-07-12 12:33:35 +08:00
Sebastien Bourdeauducq 773240bef4 hmc7043: test GPO before using 
Based on code by David.
 2018-07-12 11:30:24 +08:00
Sebastien Bourdeauducq 4843832329 hmc7043: check phase status on init. Closes #1055 
Troubleshooting by David.
 2018-07-11 19:45:24 +08:00
Sebastien Bourdeauducq 9397fa7f5a hmc7043: unstick SYSREF FSM (#1055) 
Troubleshooting by David.

Additionally, register 7D is broken.
Checking phase init state has to be done through another means.
 2018-07-11 19:11:01 +08:00
Sebastien Bourdeauducq 4f56710e4b grabber: add parser, report detected frame size in core device log 2018-07-10 02:06:37 +08:00
Robert Jördens 4eb26c0050 hmc7043: enable group 5 2018-07-03 14:16:31 +02:00
Sebastien Bourdeauducq 729ce58f98 sayma: use GTP_CLK1 to clock DRTIO satellite transceiver 
This is required to get constant skew between the DRTIO transceiver clock
(which then generates the RTIO clock) and the siphaser reference clock.

Both the Si5324 and the RTM clock tree have non-deterministic in-to-out skew
at 150MHz due to dividers.
 2018-06-28 11:23:40 +08:00
Sebastien Bourdeauducq a65721d649 sayma: put RTM clock tree into the siphaser loop 
* Fixes one bug where siphaser was one Si5324 output and the rest of the
system was clocked by the other. With the Si5324 settings we have, skew
between the outputs is not controlled.
* Puts the coaxial cable between AMC and RTM into the siphaser loop.
 2018-06-27 21:46:55 +08:00
Sebastien Bourdeauducq d49716dfac satman: tune Sayma SYSREF phases 2018-06-27 18:09:35 +08:00
Sebastien Bourdeauducq 46c044099c hmc7043,satman: verify alignment of SYSREF slips 2018-06-27 17:36:13 +08:00
Sebastien Bourdeauducq 7dfd70c502 hmc7043: make margin_{minus,plus} consistent with ad9154 2018-06-27 17:35:26 +08:00
Sebastien Bourdeauducq 4bbdd43bdf hmc7043: do not freeze if SYSREF slip fails 2018-06-27 17:32:56 +08:00
Sebastien Bourdeauducq a8a2ad68d3 runtime: tune Sayma SYSREF phases 2018-06-27 17:31:29 +08:00
Sebastien Bourdeauducq 84b3d9ecc6 bootloader: also check firmware CRC in SDRAM (#1065) 2018-06-23 11:28:12 +08:00
Sebastien Bourdeauducq 68530fde07 sayma: generate 100MHz from Si5324 on standalone and master targets 
* Allow switching between DRTIO satellite and standalone without
  touching the hardware.
* Allow operating standalone and master without an additional RF
  signal generator.
 2018-06-23 10:44:38 +08:00
whitequark b6dd9c8bb0 runtime: support builds without RTIO DMA. 
Fixes #1079.
 2018-06-23 00:56:21 +00:00
Sebastien Bourdeauducq 76fc63bbf7 jesd204: use separate controls for reset and input buffer disable 2018-06-22 11:38:18 +08:00