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556 Commits

Author SHA1 Message Date
Robert Jördens 07f5e99140 dsp/sat_add: works after previous changes 2017-06-22 18:24:22 +02:00
Robert Jördens f78d5a87e9 dsp/test: skip and fix sat_add 2017-06-22 18:01:31 +02:00
Robert Jördens 47928a2c0d sawg: disable limiter 
temporary workaround to permit testing other aspects
 2017-06-22 17:31:04 +02:00
Robert Jördens cd2ac53bc5 dsp/sat_add: make width mandatory 2017-06-22 17:28:39 +02:00
Robert Jördens 9b940aa876 dsp/sat_add: spell out logic more 2017-06-22 16:55:13 +02:00
Robert Jördens d0cf0f2b87 sawg/limiter: make signed signals explicitly 2017-06-22 13:44:36 +02:00
Robert Jördens 694f8d784c dsp/tools: unittest sat_add 2017-06-22 11:29:56 +02:00
Robert Jördens bd1438d28e sawg: wrap limits init values 2017-06-22 10:26:29 +02:00
Robert Jördens cccd01e81e sawg: cleanup sat_add logic 2017-06-22 10:26:29 +02:00
Robert Jördens 5f6e665158 test/sawg: patch delay_mu 2017-06-22 10:26:29 +02:00
Robert Jördens 570f2cc1ff dsp/tools/SatAdd: fix reuse of clipped signal 2017-06-22 10:26:29 +02:00
Robert Jördens 4b3aad2563 sawg: clean up Config 
* unify I and Q data limiters. there is no conceivable way why they
would be different.
* reorder clr bits to be like consistent
* move the sat add limiter to before the hbf again
 2017-06-22 10:26:29 +02:00
Robert Jördens f4c6879c76 sawg: special case Config RTIO address 2017-06-22 10:26:29 +02:00
Robert Jördens ff0da2c9fc sawg: stage code for y-data exchange on channels 2017-06-22 10:26:29 +02:00
Robert Jördens b6569df02f dsp/tools: clean up SatAddMixin logic 2017-06-22 10:26:29 +02:00
Sebastien Bourdeauducq 74cf074538 drtio: remove sawg_3g from example targets, add converter SPI bus from FMC-EBZ at all times 2017-06-21 17:01:52 +08:00
Robert Jördens 0d8067256b rtio: refactor RelaxedAsyncResetSynchronizer 2017-06-18 14:37:08 +02:00
Robert Jördens 424b2bfbd8 rtio: describe rio and rio_phy domains a bit more 2017-06-17 12:21:07 +02:00
Robert Jördens 219dfd8984 rtio: add one register level for rio and rio_phy resets 
* This should give Vivado some wiggle room during PnR.
* It needs three new clock domains which is ugly. But since
AsyncResetSynchronizer can only drive clock domains resets directly
there seems to be no other way to add one register level currently.
 2017-06-17 12:17:48 +02:00
Robert Jördens e19bfd4781 test_sawg_fe: add ref_multiplier to simulated core 2017-06-16 19:45:24 +02:00
Robert Jördens 2a76034fbc cri: add note about clearing of o_data 2017-06-16 19:06:00 +02:00
Robert Jördens 3f37870e25 sawg: register pre-hbf adder 2017-06-13 18:15:44 +02:00
Robert Jördens e229edd5d5 sawg: add register after hbf for timing 2017-06-12 23:08:27 +02:00
Robert Jördens 315338fca9 test/sawg: test HBF overshoot, fix sim patching 2017-06-12 20:35:47 +02:00
Robert Jördens 9a8a7b9102 sawg: handle clipping interpolator 
* give 1 bit headroom to interpolator to handle overshoot
* fix Config limiter widths (NFC)
* move clipper to behind the HBF to correctly shield DUC

This leaves a factor of two headroom for the sum of the following
effects:

  * HBF overshoot (~15 % of the step)
  * A1/A2 DDS sum

While this is technically not sufficient and can still lead to
overflows, it is unlikely that one would trigger those. It would require
doing large amplitude A1, large amplitude A2 and additionally doing
amplitude/phase jumps that would overshoot the HBF. No sane person would
try that, right?

closes #743
 2017-06-12 20:33:54 +02:00
Robert Jördens 1fb3995ffc Revert "fir/ParallelHBFUpsampler: add headroom (gain=2)" 
This reverts commit 6ac9d0c41e.

Overshooting behavior must to be handled outside the FIR.
 2017-06-12 20:07:25 +02:00
Robert Jördens 332bcc7f3b fir: check widths 2017-06-12 20:07:23 +02:00
Robert Jördens 39a1dcbb3d test/fir: look at overshoot behavior 2017-06-12 20:06:07 +02:00
Robert Jördens 6ac9d0c41e fir/ParallelHBFUpsampler: add headroom (gain=2) 
This addresses part of #743
 2017-06-12 18:59:45 +02:00
Robert Jördens bfc224d4ba phaser: adjust to new jesd 2017-05-22 19:59:53 +02:00
Robert Jördens 679060af1d phaser: enable dma 2017-05-22 19:32:34 +02:00
Robert Jördens 4901cb9a8a sawg: fix clr width 2017-05-22 17:46:55 +02:00
Robert Jördens 253ee950f6 sawg: fix config channel addr 2017-05-22 17:45:14 +02:00
Sebastien Bourdeauducq 9ab63920e0 Remove Pipistrello support 
Closes #658
Closes #381
 2017-05-15 17:17:44 +08:00
Robert Jördens 170d2886fd Merge branch 'pdq' 
* pdq:
  pdq: documentation
  pdq2 -> pdq
  pdq2: use 16 bit data, buffered read_mem()
  spi: style
  pdq2: mem_read
  pdq2: align subsequent writes to end
  sma_spi: undo cri_con
  pdq2: memory write, kernel_invariants
  sma_spi: cri/cd changes
  sma_spi: LVCMOS25
  coredevice.spi: kernel invariants and style
  sma_spi: free up user_sma pins
  sma_spi: add demo target with SPI on four SMA
  pdq2: memory write
  pdq2: crc/frame register accessors
  doc: pdq2 spi backend
  pdq2: config writes
 2017-05-12 11:46:45 +02:00
Florent Kermarrec 79c339d4ac gateware/targets/phaser: jesd core now handles jsync completely 2017-04-26 22:25:08 +02:00
Florent Kermarrec 0546affd4c gateware/target/phaser: jesd start signal renamed to jsync 2017-04-26 12:27:40 +02:00
Robert Jördens ed8edf318d sma_spi: undo cri_con 2017-04-08 17:19:35 +02:00
Robert Jördens 16b7f8f50c sma_spi: cri/cd changes 2017-04-08 17:16:19 +02:00
Robert Jördens 1e6e81a19e sma_spi: LVCMOS25 2017-04-08 17:16:19 +02:00
Robert Jördens 555b3c38c1 sma_spi: free up user_sma pins 2017-04-08 17:16:19 +02:00
Robert Jördens 2c7c6143ab sma_spi: add demo target with SPI on four SMA 2017-04-08 17:16:19 +02:00
Sebastien Bourdeauducq c2667debf8 drtio: test replace in RTL simulation 2017-04-06 16:33:59 +08:00
Sebastien Bourdeauducq 729e7b52f0 drtio: collision/replace fixes 2017-04-06 16:33:49 +08:00
Sebastien Bourdeauducq 83d87b5805 drtio: remove outdated comment 2017-04-06 12:45:10 +08:00
Sebastien Bourdeauducq c0100ebc56 rtio: fix indentation 2017-04-06 12:08:13 +08:00
Sebastien Bourdeauducq 207453efcd rtio: add a missing case for collision reporting 2017-04-06 11:28:16 +08:00
Sebastien Bourdeauducq 674bf82f3a gateware: add cri_con CSRs to all DMA-capable targets 2017-04-06 01:14:09 +08:00
Sebastien Bourdeauducq 5e3aef45dc drtio: support collision/replace + detect sequence errors at satellite 2017-04-06 01:06:56 +08:00
whitequark 17b5388259 gateware: remove one stray CRI arbiter remnant. 2017-04-05 16:38:56 +00:00