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artiq
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521 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 68530fde07 sayma: generate 100MHz from Si5324 on standalone and master targets 
* Allow switching between DRTIO satellite and standalone without
  touching the hardware.
* Allow operating standalone and master without an additional RF
  signal generator.
 2018-06-23 10:44:38 +08:00
whitequark b6dd9c8bb0 runtime: support builds without RTIO DMA. 
Fixes #1079.
 2018-06-23 00:56:21 +00:00
Sebastien Bourdeauducq 76fc63bbf7 jesd204: use separate controls for reset and input buffer disable 2018-06-22 11:38:18 +08:00
Sebastien Bourdeauducq de7d64d482 sayma: clock JESD204 from GTP CLK2 
This frees up GTP CLK1, which is routable to the SFP quads, for DRTIO.
 2018-06-21 22:33:53 +08:00
Sebastien Bourdeauducq 07bcdfd91e hmc7043: stricter check of FPGA SYSREF margin 2018-06-21 22:26:49 +08:00
Sebastien Bourdeauducq e29536351d drtio: resync SYSREF when TSC is loaded 2018-06-21 17:00:32 +08:00
Sebastien Bourdeauducq 5a2a857a2f firmware: clean up SYSREF phase management 2018-06-21 16:23:41 +08:00
Sebastien Bourdeauducq 05e908a0fd hmc7043: align SYSREF with RTIO 2018-06-21 15:54:42 +08:00
Sebastien Bourdeauducq 9741654cad hmc7043: style 2018-06-21 15:54:42 +08:00
Sebastien Bourdeauducq 45e8263208 hmc7043: do not configure phases during initial init 
They are determined later on.
 2018-06-21 15:54:42 +08:00
whitequark 7cc3da4faf firmware: do not lose the ".dirty" suffix in build versions. 
Fixes #1074.
 2018-06-21 05:18:51 +00:00
whitequark 095ee28fd9 runtime: fix size values for bytes and bytearray RPCs. 
Fixes #1076.
 2018-06-21 00:51:56 +00:00
Sebastien Bourdeauducq 814d0583db hmc7043: improve smoothness of sysref phase control 2018-06-20 17:40:48 +08:00
Sebastien Bourdeauducq 5272c11704 typo 2018-06-20 17:05:20 +08:00
Sebastien Bourdeauducq 0c32d07e8b ad9154: new sysref scan 
Print margins around the pre-defined fixed phase.
Also report error if margins are too small.

The fixed phase is also changed by this commit (the value 88 is
from before the new HMC7043 initialization code, and is probably wrong).
 2018-06-20 00:15:58 +08:00
Sebastien Bourdeauducq 3d0e92aefd hmc7043: check that chip is disabled at startup 2018-06-19 23:49:17 +08:00
Sebastien Bourdeauducq 740e6863c3 hmc7043: add delay after releasing hardware reset 2018-06-19 23:48:48 +08:00
Sebastien Bourdeauducq 75b6cea52f sayma: add SAWG to DRTIO satellite 2018-06-19 19:12:10 +08:00
Sebastien Bourdeauducq eb3259b847 firmware: reduce number of DAC initialization attempts 
Faster startup when one DAC is broken.
 2018-06-19 19:10:23 +08:00
Sebastien Bourdeauducq 1d594d0c97 firmware: make DAC initialization failures non-fatal 
This allows using RTMs with one broken DAC for development.
 2018-06-19 19:09:38 +08:00
Sebastien Bourdeauducq 158b5e3083 satman: program Allaki 2018-06-19 18:09:05 +08:00
Sebastien Bourdeauducq 574892a4e5 firmware/serwb: cleanup and improve messaging 2018-06-19 15:11:03 +08:00
Sebastien Bourdeauducq c862471165 typo 2018-06-19 14:35:24 +08:00
Sebastien Bourdeauducq 433273dd95 sayma: support RTM FPGA, HMC830 and HMC7043 in DRTIO master and satellite 2018-06-19 14:33:48 +08:00
Sebastien Bourdeauducq 476cfa0f53 si5324: improve lock messaging 2018-06-19 14:29:57 +08:00
Sebastien Bourdeauducq d29b3dd588 hmc830: compile-time configurable reference frequency 2018-06-19 13:47:32 +08:00
Sebastien Bourdeauducq 0e640a6d6f hmc7043: fix SYSREF to meet s/h at FPGA (#794) 2018-06-18 17:04:12 +08:00
Robert Jördens 6272052d15 ad9154: don't drive the bsm with txen pins 2018-06-18 10:04:42 +02:00
Sebastien Bourdeauducq 4f0c918dd3 slave_fpga: improve messaging 2018-06-17 00:27:27 +08:00
Robert Jördens 40baa8ecba hmc7043: disable ch 10 and 11 group 2018-06-15 15:34:31 +00:00
Robert Jördens edfae3c4ba hmc7043: make fpga fabric clocks lvds 
2 V common and 1.9 Vpp swing
is brutal to the banks (HP 1.8V AMC and RT 1.8V RTM)
 2018-06-15 14:24:33 +00:00
Robert Jördens f385add8b1 slave_fpga: disable cclk and din drive when done 
to guard against accidental contention (old rtm gateware
but #813 rework done)
 2018-06-13 16:26:48 +00:00
Robert Jördens a9a25f2605 sayma_rtm: drive ref_lo_clk_sel, and set clk muxes early 2018-06-12 20:00:12 +02:00
Thomas Harty b90a8fcc82 Merge branch 'master' of https://github.com/m-labs/artiq 2018-06-12 14:55:22 +01:00
ion 28ecf81c6c Sayma: HMC7043 init and detect no longer need results. 2018-06-12 13:10:26 +01:00
ion c8935f7adf Sayma: bypass dividers where possible to minimize noise (nb this changes the output skew). 2018-06-12 12:56:04 +01:00
hartytp 7a0140ecb2
Sayma HMC830: update interface and register writes. (#1068) 
* Break the HMC830 init into separate functions for general purpose (but, integer-N) init, setting dividers and checking lock

* Use 1.6mA ICP (which the loop filter was optimized for)

* Go through the data sheet carefully and set all registers to the correct value (e.g. ensure that all settings are correctly optimized for integer-N usage)

* Change divider values (now using 100MHz PFD, which should give lower noise in theory)
 2018-06-12 12:37:17 +01:00
Robert Jördens a9d97101fc slave_fpga: add another check 2018-06-12 10:24:04 +02:00
Robert Jördens a143e238a8 savel_fpga: get rid of unneeded config 2018-06-12 10:24:04 +02:00
Robert Jördens 4912f53ab4 slave_fpga: board_misoc 2018-06-12 10:24:04 +02:00
hartytp cb6e44b23a Sayma: disable unused HMC7043 outputs. 2018-06-12 16:18:20 +08:00
Sebastien Bourdeauducq af88c4c93e clean up hmc7043 reset 2018-06-05 20:41:48 +08:00
Thomas Harty 988054f4bb Sayma: fix mistake in HMC7043 init code. 2018-06-05 19:22:04 +08:00
Thomas Harty bd1ac7cf3b Configure HMC7043 to give deterministic phase differences between its outputs 2018-06-05 19:22:04 +08:00
Thomas Harty ac5c4913ec Sayma RTM: hold hmc7043 in reset/mute state during init. 2018-06-05 19:22:04 +08:00
Florent Kermarrec b82158a2de firmware/ad9154: add stpl test 2018-06-05 02:08:57 +02:00
Florent Kermarrec 925b47b077 firmware/ad9154: reset the dac between each configuration attempt 2018-06-04 14:03:26 +02:00
whitequark d686d33093 runtime: print hex dumps around PC/EA in case of exception. 
For #1026.
 2018-06-01 21:17:59 +00:00
whitequark 2e09307d8d firmware: use writeln instead of write in UART logger. 2018-05-29 03:16:52 +00:00
Sebastien Bourdeauducq 560889372f firmware: grabber support 2018-05-29 10:26:36 +08:00