Commit Graph

17 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 0b437c7645 conda: shorten git hash in strings to 8 characters instead of 12 2017-06-05 11:43:10 +08:00
whitequark d383145752 conda: use GIT_FULL_HASH rather than GIT_DESCRIBE_HASH. 2017-04-20 16:58:38 +00:00
whitequark c9b20a1765 Commit missing parts of 0d0ddf2e. 2017-04-20 16:53:16 +00:00
whitequark 0d0ddf2e58 conda: limit git hashes in build numbers to 8 chars exactly.
Before this commit, a nasty edge case was possible where repositories
on different builders have had different sets of objects fetched
into them, and so git-describe selected different lengths for
abbreviating hashes.

See also https://github.com/conda/conda-build/issues/1940.
2017-04-20 16:40:10 +00:00
whitequark 3de19f6786 conda: use verbose misoc build. 2017-02-05 14:26:08 +00:00
Robert Jördens fb56c32d35 conda: use artiq-dev metapackage 2017-02-01 15:34:05 +01:00
whitequark c585784cd9 conda: bump misoc dependency. 2017-01-30 08:03:41 +00:00
Sebastien Bourdeauducq bff5f1b714 conda: update migen 2017-01-30 13:39:44 +08:00
Robert Jördens 9e92706d09 conda: pin misoc/migen package hashes 2017-01-27 14:43:24 +01:00
whitequark c45a170bb4 firmware: update for Rust 1.16.0. 2016-12-26 17:20:29 +00:00
Robert Jördens ca636ef28a conda/phaser: build-depend on numpy 2016-12-08 16:23:40 +01:00
Robert Jördens 7657cf1264 phaser: bump misoc/migen 2016-11-29 14:55:15 +01:00
Robert Jördens 41779367b5 phaser: adapt conda recipe 2016-11-24 16:04:13 +01:00
Robert Jördens 7664b226f2 phaser/conda: bump jesd204b 2016-11-18 15:34:03 +01:00
Robert Jördens 062aca2a6b conda/phaser: build-depend on jesd204b 2016-10-19 14:44:54 +02:00
Robert Jördens 81511feab8 phaser: README: specify versions 2016-10-12 17:13:06 +02:00
Robert Jördens 4a0eaf0f95 phaser: add jesd204b rtio dds
gateware: add jesd204b awg

gateware: copy phaser (df3825a)
dsp/tools: update satadd mixin
phaser: no DDS stubs
dsp: accu fix
phaser: cleanup/reduce

sawg: kernel support and docs

sawg: coredevice api fixes

sawg: example ddb/experiment

phaser: add conda package

examples/phaser: typo

sawg: adapt tests, fix accu stb

sawg: tweak dds parameters

sawg: move/adapt/extend tests

sawg: test phy, refactor

phaser: non-rtio spi

phaser: target cli update

phaser: ad9154-fmc-ebz pins

phaser: reorganize fmc signal naming

phaser: add test mode stubs

phaser: txen is LVTTL

phaser: clk spi xfer test

phaser: spi for ad9154 and ad9516

phaser: spi tweaks

ad9154: add register map from ad9144.xml

ad9516: add register map from ad9517.xml and manual adaptation

ad9154_reg: just generate getter/setter macros as well

ad9154: reg WIP

ad9154: check and fix registers

kc705: single ended rtio_external_clk

use single ended user_sma_clk_n instead of p/n to free up one clock sma

kc705: mirror clk200 at user_sma_clock_p

ad9516_regs.h: fix B_COUNTER_MSB

phase: wire up clocking differently

needs patched misoc

kc705: feed rtio_external_clock directly

kc705: remove rtio_external_clk for phaser

phaser: spi tweaks

ad9516: some startup

ad9516_reg fixes

phaser: setup ad9516 for supposed 500 MHz operation

ad9516: use full duplex spi

ad9154_reg: add CONFIG_REG_2

ad9154_reg: fixes

phaser: write some ad9154 config

ad9154_reg: fixes

ad9154: more init, and human readable setup

ad9154/ad9516: merge spi support

ad9154: status readout

Revert "kc705: remove rtio_external_clk for phaser"

This reverts commit d500288bb44f2bf2eeb0c2f237aa207b0a8b1366.

Revert "kc705: feed rtio_external_clock directly"

This reverts commit 8dc7825519e3e75b7d3d29c9abf10fc6e3a8b4c5.

Revert "phase: wire up clocking differently"

This reverts commit ad9cc450ffa35abb54b0842d56f6cf6c53c6fbcc.

Revert "kc705: mirror clk200 at user_sma_clock_p"

This reverts commit 7f0dffdcdd28e648af84725682f82ec6e5642eba.

Revert "kc705: single ended rtio_external_clk"

This reverts commit a9426d983fbf5c1cb768da8f1da26d9b7335e9cf.

ad9516: 2000 MHz clock

phaser: test clock dist

phaser: test freqs

ad9154: iostandards

phaser: drop clock monitor

phaser: no separate i2c

phaser: drive rtio from refclk, wire up sysref

phaser: ttl channel for sync

ad9154: 4x interp, status, tweaks

phaser: sync/sysref 33V banks

phaser: sync/sysref LVDS_25 inputs are VCCO tolerant

phaser: user input-only ttls

phaser: rtio fully from refclk

ad9154: reg name usage fix

ad9154: check register modifications

Revert "ad9154: check register modifications"

This reverts commit 45121d90edf89f7bd8703503f9f317ad050f9564.

ad9154: fix status code

ad9154: addrinc, recal serdes pll

phaser: coredevice, example tweaks

sawg: missing import

sawg: type fixes

ad9514: move setup functions

ad9154: msb first also decreasing addr

phaser: use sys4x for rtio internal ref

phaser: move init code to main

phaser: naming cleanup

phaser: cleanup pins

phaser: move spi to kernel cpu

phaser: kernel support for ad9154 spi

ad9154: add r/w methods

ad9154: need return annotations

ad9154: r/w methods are kernels

ad9154_reg: portable helpers

phaser: cleanup startup kernel

ad9154: status test

ad9154: prbs test

ad9154: move setup, document

phaser: more documentation
2016-10-05 16:17:50 +02:00