pca006132
da4ff44377
compiler: fixed try codegen and allocate exceptions
...
Exceptions are now allocated in the runtime when we raise the exception,
and destroyed when we exit the catch block. Nested exception and try
block is now supported, and should behave the same as in CPython.
Exceptions raised in except blocks will now unwind through finally
blocks, matching the behavior in CPython. Reraise will now preserve
backtrace.
Phi block LLVM IR generation is modified to handle landingpads, which
one ARTIQ IR will map to multiple LLVM IR.
2022-01-26 07:16:54 +08:00
pca006132
4644e105b1
compiler: modified exception representation
...
Exception name is replaced by exception ID, which requires no
allocation. Other strings in the exception can now be 'host-only'
strings, which is represented by a CSlice with len = usize::MAX and
ptr = key, to avoid the need for allocation when raising exceptions
through RPC.
2022-01-26 07:16:54 +08:00
hartytp
715bff3ebf
Revert "Merge pull request #1544 from airwoodix/dataset-compression" ( #1838 )
...
* Revert "Merge pull request #1544 from airwoodix/dataset-compression"
This reverts commit 311a818a49
, reversing
changes made to 7ffe4dc2e3
.
* fix accidental revert of f42bea06a8
2022-01-25 10:02:15 +08:00
Steve Fan
3f812c4c2c
comm_kernel: fix RPC exception handling ( #1801 )
2022-01-12 15:23:37 +08:00
Steve Fan
de5892a00a
comm_kernel: check if elements are within bounds for RPC list ( #1824 )
2022-01-11 17:16:45 +08:00
Peter Drmota
4eee49f889
gateware.test.suservo: Fix tests for python >=3.7
...
Closes #1748
2022-01-11 17:16:09 +08:00
occheung
9eee0e5a7b
gateware/suservo: fix profile no. in test
...
Follow-up/Test update for 9d49302
.
2022-01-11 14:20:47 +08:00
Steve Fan
d7dd75e833
comm_kernel: fix off-by-one error for numeric value range check
2022-01-11 10:13:42 +08:00
Spaqin
095fb9e333
add Almazny support ( #1780 )
2022-01-11 09:55:39 +08:00
Sebastien Bourdeauducq
4e3e0d129c
firmware: fix compilation warning
2022-01-11 09:31:26 +08:00
pca006132
12ee326fb4
firmware: fixed personality function
2022-01-11 09:30:19 +08:00
occheung
61349f9685
sinara_tester: fix outdated API
2022-01-10 17:23:28 +08:00
occheung
cea0a15e1e
suservo: use default urukul profile
2022-01-10 16:21:39 +08:00
occheung
8b45f917d1
urukul: use default profile
2022-01-10 16:21:39 +08:00
pca006132
6542b65db3
compiler: fixed exception codegen issues
2022-01-10 15:54:29 +08:00
pca006132
9f90088fa6
compiler: generate appropriate landingpad IR
...
When used together with modified personality function, we got ~20%
performance improvement in exception unwinding with zynq.
2022-01-10 15:54:29 +08:00
occheung
5e1847e7c1
compiler: rename `variables` to `retainedNodes`
...
Part of the changes that was made to LLVM 6 by the time that LLVM 7 was released.
LLVM commit: 2c864551df
LLVM differential review: https://reviews.llvm.org/D45024
2022-01-10 11:28:37 +08:00
occheung
6f3c49528d
compiler: revert cabe5ac
...
The lack of debug emitter causes #1821 .
2022-01-10 11:26:03 +08:00
Sebastien Bourdeauducq
eaa1505c94
update documentation ( #1820 )
2022-01-08 11:55:52 +08:00
Leon Riesebos
f42bea06a8
worker_db: removed warning for writing a dataset that is also in the archive
...
Signed-off-by: Leon Riesebos <leon.riesebos@duke.edu>
2022-01-08 11:48:18 +08:00
occheung
9d493028e5
gateware/suservo: write to profile 7
...
Fixes #1817 .
2022-01-07 16:41:19 +08:00
Sebastien Bourdeauducq
bbac477092
tools: fix importlib issue
2021-12-21 13:20:11 +08:00
Steve Fan
c0a7be0a90
llvm_ir: move stacksave before lltag alloca in build_rpc
...
Signed-off-by: Steve Fan <sf@m-labs.hk>
2021-12-19 00:07:07 +00:00
Sebastien Bourdeauducq
9e5e234af3
stop using explicit ProactorEventLoop on Windows
...
It is now the default in Python.
2021-12-14 20:06:38 +08:00
Sebastien Bourdeauducq
352317df11
test_dataset_db: remove (too much breakage on Windows)
2021-12-14 19:27:15 +08:00
Sebastien Bourdeauducq
a518963a47
test_dataset_db: disable tests broken on windows
2021-12-14 19:19:22 +08:00
Sebastien Bourdeauducq
37f14d94d0
test_dataset_db: fix for windows
2021-12-14 19:07:17 +08:00
Peter Drmota
7c664142a5
Simplified use of the AD9910 RAM feature ( #1584 )
...
* coredevice: Change Urukul default single-tone profile to 7
This allows using the internal profile control in RAM modulation mode (which always starts to play back at profile 0) without competing for the content of the profile 0 register used in single tone mode.
Signed-off-by: Peter Drmota <peter.drmota@physics.ox.ac.uk>
* ad9910/set_mu: comment on caveats when setting register
* ad9910: avoid unnecessary write/param
Credit: Solution proposed by @pmldrmota in https://github.com/m-labs/artiq/pull/1584#issuecomment-987774353
* revert 1064fdff
(`set_mu()` comments)
158a7be7
had addressed this issue.
Co-authored-by: occheung <dc@m-labs.hk>
2021-12-13 23:44:03 +08:00
Etienne Wodey
33a9ca2684
tools/file_import: use SourceFileLoader
...
This allows loading modules from files with extensions not in
importlib.machinery.SOURCE_SUFFIXES
Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
2021-12-09 11:47:04 +08:00
Sébastien Bourdeauducq
1def0d98c5
Merge branch 'master' into dataset-compression
2021-12-06 12:40:30 +08:00
Leon Riesebos
7ffe4dc2e3
coredevice: set default pow for ad9912 set_mu()
2021-12-06 12:34:55 +08:00
Leon Riesebos
9e3ea4e8ef
coredevice: fixed type annotations for AD9910
2021-12-06 12:34:55 +08:00
Steve Fan
4a6bea479a
Host report for async error upon kernel termination ( #1791 )
...
Closes #1644
2021-12-04 13:33:24 +08:00
mwojcik
7953f3d705
kc705: add drtio 100mhz clk switch
2021-12-03 17:19:11 +08:00
mwojcik
f281112779
satman: add 100mhz si5324 settings
...
siphaser: add calculated vco for 100mhz comment
2021-12-03 17:19:11 +08:00
mwojcik
eec3ea6589
siphaser: add support for 100mhz rtio
2021-12-03 17:19:11 +08:00
Etienne Wodey
9f830b86c0
kasli: add SED lanes count option to HW description JSON file ( #1745 )
...
Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
2021-12-03 17:05:35 +08:00
Sebastien Bourdeauducq
b8e7add785
language: remove deprecated set_dataset(..., save=...)
2021-12-01 22:41:34 +08:00
David Nadlinger
c6039479e4
compiler: Add lit test for call site attributes [nfc]
2021-11-27 04:46:07 +00:00
David Nadlinger
63b5727a0c
compiler: Also emit byval argument attributes at call sites
...
See previous commit.
GitHub: Fixes #1599 .
2021-11-27 04:45:50 +00:00
David Nadlinger
9b01db3d11
compiler: Emit sret call site argument attributes
...
LLVM 6 seemed not to mind the mismatch, but more recent
versions produce miscompilations without this.
Needs llvmlite support (GitHub: numba/llvmlite#702 ).
2021-11-27 04:44:41 +00:00
Sebastien Bourdeauducq
6a433b2fce
artiq_sinara_tester: test Urukul attenuator digital control
2021-11-24 18:57:16 +08:00
occheung
9423428bb0
drtio: fix crc32 offset address
2021-11-24 12:00:56 +08:00
Harry Ho
b49f813b17
artiq_flash: ignore checking non-RTM artifacts if unused
2021-11-18 16:59:32 +08:00
Peter Drmota
20e079a381
AD9910 driver feature extension and SUServo IIR readability ( #1500 )
...
* coredevice.ad9910: Add set_cfr2 function and extend arguments of set_cfr1 and set_sync
* SUServo: Wrap CPLD and DDS devices in a list
* SUServo: Refactor [nfc]
Co-authored-by: drmota <peter.drmota@physics.ox.ac.uk>
Co-authored-by: David Nadlinger <code@klickverbot.at>
2021-11-15 12:09:16 +08:00
occheung
db3e5e83e6
bump misoc
2021-11-08 16:59:08 +08:00
occheung
09945ecc4d
gateware: fix drtio/dma tests
2021-11-08 16:59:08 +08:00
occheung
02119282b8
build_soc: build VexRiscv_G if not kasli v1.x
2021-11-08 16:59:08 +08:00
occheung
750b0ce46d
ddb_temp: select appropriate compiler target
2021-11-08 16:59:08 +08:00
occheung
531670d6c5
dyld: check ABI
2021-11-08 16:59:08 +08:00
occheung
0f660735bf
ll_gen: adjust csr address by detecting target class
2021-11-08 16:59:08 +08:00
occheung
0755757601
compiler/tb: use FPU
2021-11-08 16:59:08 +08:00
occheung
0d708cd61a
compiler/target: split RISCV target into float/non-float
2021-11-08 16:59:08 +08:00
occheung
03b803e764
firmware: adjust csr separation
2021-11-08 16:59:08 +08:00
occheung
b3e315e24a
rust: find json file using CARGO_TRIPLE
2021-11-08 16:59:08 +08:00
occheung
0898e101e2
board_misoc: reuse riscv dir for comm & kernel
2021-11-08 16:59:08 +08:00
occheung
cb247f235f
gateware: pass adr_w/data_w to submodules
2021-11-08 16:59:08 +08:00
occheung
90f944481c
kernel_cpu: add fpu if not kasli v1.x
2021-11-08 16:59:08 +08:00
occheung
d84ad0095b
comm_cpu: select 64b bus if not kasli v1.x
2021-11-08 16:59:08 +08:00
occheung
dd68b4ab82
mailbox: parametrize address width
2021-11-08 16:59:08 +08:00
occheung
c6e0e26440
drtio: accept 32b/64b bus
2021-11-08 16:59:08 +08:00
occheung
8da924ec0f
dma: set conversion granularity using bus width
2021-11-08 16:59:08 +08:00
Robert Jördens
591507a7c0
Merge pull request #1774 from m-labs/fastino-cic
...
Fastino cic
2021-10-28 17:44:20 +02:00
Robert Jördens
5a5b0cc7c0
fastino: expand docs
2021-10-28 15:19:48 +00:00
Spaqin
69cddc6b86
rtio_clocking: add warnings for unsupported rtio_clock settings ( #1773 )
2021-10-28 16:34:22 +08:00
Spaqin
9b1d7e297d
runtime: clock input specification improvements
...
closes #1735
2021-10-28 16:21:51 +08:00
Robert Jördens
1ff474893d
Revert "fastino: make driver filter order configurable"
...
This reverts commit 10c37b87ec
.
2021-10-28 06:29:56 +00:00
Robert Jördens
10c37b87ec
fastino: make driver filter order configurable
2021-10-27 20:24:58 +00:00
Harry Ho
c940f104f1
artiq_flash: fix gateware header not in little-endian for RISC-V
2021-10-25 11:20:26 +08:00
Harry Ho
0aa8a739aa
sayma_rtm: fix RTM firmware not in little-endian for RISC-V
2021-10-25 11:20:26 +08:00
occheung
d5fa3d131a
cargo.lock: update libc version for libfringe
2021-10-16 17:42:24 +08:00
occheung
6d3164a912
riscv: print mtval on panic
2021-10-16 17:42:24 +08:00
occheung
46326716fd
runtime: bump libfringe, impl ecall abi
...
See libfringe PR: M-Labs/libfringe#1
2021-10-16 17:42:24 +08:00
occheung
0a59c889de
satman/kern: init locked PMP on startup
2021-10-16 17:42:24 +08:00
occheung
27a7a96626
runtime: setup pmp + transfer to user
2021-10-16 17:42:24 +08:00
occheung
a0bf11b465
riscv: impl pmp
2021-10-16 17:42:24 +08:00
occheung
790a20edf6
linker: generate stack guard + symbol
2021-10-16 17:42:24 +08:00
fanmingyu212
178a86bcda
master: add an argument to set an experiment subdirectory
...
Signed-off-by: Mingyu Fan <mingyufan@ucsb.edu>
2021-10-15 16:54:31 +08:00
Sebastien Bourdeauducq
35d21c98d3
Revert "runtime: expose rint from libm"
...
Consistency with NAR3/Zynq where rint is not available.
This reverts commit f5100702f6
.
2021-10-11 08:12:04 +08:00
Sebastien Bourdeauducq
f5100702f6
runtime: expose rint from libm
2021-10-10 20:40:17 +08:00
Sebastien Bourdeauducq
3c1cbf47d2
phaser: add more slack during init. Closes #1757
2021-10-10 16:18:55 +08:00
Robert Jördens
3f6bf33298
fastino: add interpolator support
2021-10-08 15:47:07 +00:00
occheung
59065c4663
alloc_list: support alloc w/ large align
...
Signed-off-by: Oi Chee Cheung <dc@m-labs.hk>
2021-10-07 12:38:03 +08:00
Spaqin
1894f0f626
gateware: share RTIOClockMultiplier and fix_serdes_timing_path ( #1760 )
2021-10-07 08:19:38 +08:00
Etienne Wodey
a8333053c9
sinara_tester: add device_db and test selection CLI options
...
Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
2021-09-27 17:44:50 +08:00
Sebastien Bourdeauducq
3ed10221d8
compiler: remove big-endian support. Closes #1590
2021-09-13 13:40:24 +08:00
Sebastien Bourdeauducq
e8a7a8f41e
compiler: work around idiotic windoze behavior that causes conda ld.lld not to be found
2021-09-13 10:40:54 +08:00
Sebastien Bourdeauducq
ffb1e3ec2d
wavesynth: np.int is deprecated
2021-09-13 07:02:35 +08:00
Sebastien Bourdeauducq
2d79d824f9
firmware: remove minor or1k leftovers
2021-09-12 20:03:37 +08:00
occheung
a573dcf3f9
board_misoc/build: use rv32 as target arg
...
The original rv64 argument was only to match the misoc counterpart.
2021-09-10 14:11:23 +08:00
occheung
448974fe11
runtime/main: cleanup
2021-09-10 13:59:53 +08:00
occheung
b091d8cb66
kernel: flush cache before mod_init
...
This could be necessary as redirecting instructions from D$ directly to I$ as it seems.
Related: https://github.com/SpinalHDL/VexRiscv/issues/137
2021-09-10 13:25:12 +08:00
occheung
5394d04669
test_spi: add delay
2021-09-10 13:25:12 +08:00
occheung
b8ed5a0d91
alloc: fix alignment for riscv32 arch
2021-09-10 13:25:12 +08:00
occheung
2213e7ffac
ksupp/rtio/exception: fix timestamp
2021-09-10 13:25:12 +08:00
occheung
09ffd9de1e
dma: fix timestamp fetch
2021-09-10 13:25:12 +08:00
occheung
051a14abf2
rtio/dma: fix endianness
2021-09-10 13:25:12 +08:00
occheung
c6ba0f3cf4
ksupport: fix dma cslice (ffi)
2021-09-10 13:25:12 +08:00
occheung
c812a837ab
runtime: enlarge stack size
2021-09-10 13:25:12 +08:00
occheung
a596db404d
satman: fix cargo xbuild sysroot
2021-09-10 13:25:12 +08:00
occheung
4fab267593
cargo: std dependency hack
2021-09-10 13:25:12 +08:00
occheung
dcbd9f905c
cargo: use cargo xbuild
2021-09-10 13:25:12 +08:00
occheung
9f6b3f6014
firmware: clarify target triple
...
The lack of compressed instruction support can be inferred from the target triple, literally.
2021-09-10 13:25:12 +08:00
occheung
4619a33db4
test: remove broken array return tests
...
Removed test cases that do not respect lifetime/scope constraint.
See discussion in artiq-zynq repo: M-Labs/artiq-zynq#119
Referred to the patch from @dnadlinger. 5faa30a837
2021-09-10 13:25:12 +08:00
occheung
5985f7efb5
syscall: lower nowrite to inaccessiblememonly
...
In the origin implementation, the `nowrite` flag literally means not writing memory at all.
Due to the usage of flags on certain functions, it results in the same issues found in artiq-zynq after optimization passes. (M-Labs/artiq-zynq#119 )
A fix wrote by @dnadlinger can resolve this issue. (c1e46cc7c8
)
2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq
6db7280b09
flake: board package WIP
2021-09-10 13:25:12 +08:00
occheung
d8ac429059
dyld: streamline lib.rs
...
Only riscv32 is supported anyway, no need to have excessive architecture check.
2021-09-10 13:25:12 +08:00
occheung
798774192d
slave_fpga/bootloader: read in little endian
2021-09-10 13:25:12 +08:00
occheung
eecd825d23
firmware: suppress warning
2021-09-10 13:25:12 +08:00
occheung
1da0554a49
pcr: purge
2021-09-10 13:25:12 +08:00
occheung
5d0a8cf9ac
llvm_ir_gen: fix indent
2021-09-10 13:25:12 +08:00
occheung
70507e1b72
Cargo.lock: update
2021-09-10 13:25:12 +08:00
occheung
c113cd6bf5
libfringe: bump
2021-09-10 13:25:12 +08:00
occheung
61b0170a12
firmware: purge or1k
2021-09-10 13:25:12 +08:00
occheung
af263ffe1f
ksupport: fix rpc, cache signature (FFI)
...
The reason of the borrow stuff is explained in M-Labs/artiq-zynq#76 (artiq-zyna repo).
As for `cache_get()`, compiler will perform stack allocation to pre-allocate the returned structure, and pass to cache_get alongside the `key`.
However, ksupport fails to recognize the passed memory, so it will always assume the passed memory as the key.
2021-09-10 13:25:12 +08:00
occheung
a833974b50
analyzer: fix endianness
2021-09-10 13:25:12 +08:00
occheung
d623acc29d
llvm_ir_gen: fix now with now_pinning & little-endian target
2021-09-10 13:25:12 +08:00
occheung
8fa47b8119
rpc: enforce alignment
2021-09-10 13:25:12 +08:00
occheung
de0f2d4a28
firmware: adopt endianness protocol in artiq-zynq
...
Related:
artiq-zynq: M-Labs/artiq-zynq#126
artiq: #1588
2021-09-10 13:25:12 +08:00
occheung
9afe63c08a
ksupport: fix proto_artiq dependency
2021-09-10 13:25:12 +08:00
occheung
29a2f106d1
ksupport: replace asm with llvm_asm
2021-09-10 13:25:12 +08:00
occheung
b30ed75e69
kernel.ld: load elf header and prog headers
...
ld.lld has a habit of not putting the headers under any load sections.
However, the headers are needed by libunwind to handle exception raised by the kernel.
Creating PT_LOAD section with FILEHDR and PHDRS solves this issue. Other PHDRS are also specified as linkers (not limited to ld.lld) will not create additional unspecified headers even when necessary.
2021-09-10 13:25:12 +08:00
occheung
279593f984
ksupport.ld: merge sbss with bss
2021-09-10 13:25:12 +08:00
occheung
1ba8c8dfee
runtime: remove irq again
2021-09-10 13:25:12 +08:00
occheung
3d629006df
makefiles: revert byte-swaps
2021-09-10 13:25:12 +08:00
occheung
7542105f0f
board_misoc: remove pcr
...
VexRiscv seems to not support additional hardware performance counter, at least I have not seen any documentation on how to use it.
2021-09-10 13:25:12 +08:00
occheung
01ca114c66
runtime: remove irq dependency
2021-09-10 13:25:12 +08:00
occheung
36171f2c61
runtime: remove inaccurate sp on panic
2021-09-10 13:25:12 +08:00
occheung
01e357e5d3
ksupport.ld: reduce load section alignment
2021-09-10 13:25:12 +08:00
occheung
f77b607b56
compiler: generate symbols
2021-09-10 13:25:12 +08:00
occheung
1293e0750e
ld, makefiles: use ld.lld
2021-09-10 13:25:12 +08:00
occheung
fc42d053d9
kernel: use vexriscv
2021-09-10 13:25:12 +08:00
occheung
1b516b16e2
targets: default to vexriscv cpu
2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq
e8fe8409b2
libartiq_support: compatibility with recent stable rustc
2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq
cabe5ace8e
compiler: remove DebugInfoEmitter for now
...
Causes problems with LLVM 9 and not needed at first.
2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq
6629a49e86
compiler: use LLVM binutils/linker for Arm as well
...
Previously we kept GNU Binutils because they are less of a pain to support
on Windoze - the source of so many problems - but with RISC-V we need to
update LLVM anyway.
2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq
43d120359d
compiler: switch to upstream llvmlite and RISC-V target
2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq
5656e52581
remove profiler
2021-09-10 13:25:12 +08:00
occheung
1b8b4baf6a
ksupport: fix panic, libc, unwind
2021-09-10 13:25:12 +08:00
occheung
905330b0f1
ksupport: handle riscv exceptions
2021-09-10 13:25:12 +08:00
occheung
50a62b3d42
liballoc: change align to 16 bytes
2021-09-10 13:25:12 +08:00
occheung
7f0bc9f7f0
runtime/makefile: specify emulation, flip endianness
2021-09-10 13:25:12 +08:00
occheung
c42adfe6fd
runtime.ld: merge .sbss & .bss
2021-09-10 13:25:12 +08:00
occheung
f56152e72f
rust: fix dependencies
2021-09-10 13:25:12 +08:00
occheung
c800b6c8d3
runtime: update rust alloc, managed
2021-09-10 13:25:09 +08:00
occheung
e99061b013
runtime: add riscv
2021-09-10 13:23:22 +08:00
occheung
ecedec577c
runtime: impl riscv exception handling
2021-09-10 13:23:15 +08:00
occheung
252594a606
runtime: impl riscv panic handler
2021-09-10 13:20:31 +08:00
occheung
31bf17563c
personality: update from rust/panic_unwind
2021-09-10 13:20:31 +08:00
occheung
bfddd8a30f
libdyld: add riscv support
2021-09-10 13:20:31 +08:00