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134 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 82def6b535 grabber: add frequency counter 
Cameras are a bit obscure about what they output, this can help with troubleshooting.
 2018-07-12 17:05:18 +08:00
Sebastien Bourdeauducq 4f56710e4b grabber: add parser, report detected frame size in core device log 2018-07-10 02:06:37 +08:00
Sebastien Bourdeauducq 2612fd1e72 rtio: add grabber deserializer and WIP PHY encapsulation 2018-05-28 22:42:27 +08:00
Sebastien Bourdeauducq 3027951dd8 integrate new AD9914 driver 
moninj, analyzer, docs, examples, tests.
 2018-05-13 23:29:35 +08:00
Robert Jördens f055bf88f6 suservo: add clip flags (#992) 2018-05-09 07:16:15 +00:00
Robert Jördens 5f00326c65 suservo: coeff mem write port READ_FIRST 2018-04-27 15:43:32 +00:00
Robert Jördens 307cd07b9d suservo: lots of gateware/ runtime changes 
tested/validated:

* servo enable/disable
* dds interface, timing, io_update, mask_nu
* channel control (en_out, en_iir, profile)
* profile configuration (coefficients, delays, offsets, channel)
* adc timings and waveforms measured
* asf state readback
* adc readback

individual changes below:

suservo: correct rtio readback

suservo: example, device_db [wip]

suservo: change rtio channel layout

suservo: mem ports in rio domain

suservo: sck clocked from rio_phy

suservo: cleanup, straighten out timing

suservo: dds cs polarity

suservo: simplify pipeline

suservo: drop unused eem names

suservo: decouple adc SR from IIR

suservo: expand coredevice layer

suservo: start the correct stage

suservo: actually load ctrl

suservo: refactor/tweak adc timing

suservo: implement cpld and dds init
 2018-04-27 13:50:26 +02:00
Robert Jördens c83305065a suservo: add servo/config/status register 2018-04-25 15:59:06 +00:00
Robert Jördens fe75064c1e suservo: cleanup rtio interface 2018-04-24 13:08:40 +00:00
Robert Jördens 99dd9c7a2a suservo: fix rtio interface width 2018-04-23 18:30:18 +00:00
Robert Jördens 934c41b90a gateware: add suservo 
from
fe4b60b902

m-labs/artiq#788
 2018-04-23 18:24:59 +00:00
Robert Jördens 3a0dfb7fdc ad53xx: port monitor, moninj dashboard, kc705 target 2018-03-24 16:04:02 +01:00
Sebastien Bourdeauducq f8c2d54e75 ttl_serdes_ultrascale: configurable SERDES ratio. Also try X4 on Sayma 2018-03-21 13:01:38 +08:00
Sebastien Bourdeauducq c8020f6bbd ttl_serdes_generic: fix/upgrade test 2018-03-20 16:46:57 +08:00
Sebastien Bourdeauducq a5825184b7 add ttl_serdes_ultrascale (untested) 2018-03-20 16:07:23 +08:00
Sebastien Bourdeauducq fad066f1aa ttl_serdes_7series: cleanup indentation 
Inconsistent with other code and confuses text editors.
 2018-03-20 15:50:04 +08:00
Sebastien Bourdeauducq a315ecd10b rtio/ttl_serdes_7series: reset IOSERDES (#958) 2018-03-14 09:01:29 +08:00
Chris Ballance 6dfebd54dd ttl_serdes_7series: use correct IBUFDS_INTERMDISABLE port names 2018-03-12 10:37:33 +08:00
Robert Jördens b0282fa855 spi2: reset configuration in rio_phy 2018-03-07 14:42:11 +00:00
Robert Jördens 50298a6104 ttl_serdes_7series: suppress diff_term in outputs 2018-03-06 14:27:19 +01:00
Robert Jördens e356150ac4 ttl_simple: support differential io 2018-03-06 14:27:19 +01:00
Robert Jördens cc70578f1f remove old spi RTIO Phy 2018-03-01 11:19:18 +01:00
Robert Jördens f8e6b4f4e3 ad5360: port to spi2 
* kc705 nist_clock target gateware
* coredevice driver
* moninj code
* test/example/device_db

This is untested as we don't have a AD5360 board right now.
Will be tested with Zotino v1.1

m-labs/artiq#926
 2018-02-22 10:25:46 +01:00
Robert Jördens 37a0d6580b spi2: add RTIO gateware and coredevice driver 
1006218997
 2018-02-21 13:37:36 +00:00
Robert Jördens 7a1d71502a ttl_serdes_7series: drive IBUF and INTERM disables from serdes 2018-02-21 13:37:29 +00:00
Robert Jördens 476e4fdd56 ttl_serdes_7series: disable IBUF and INTERM when output 2018-02-21 13:37:29 +00:00
Robert Jördens 6d20b71dde ttl_serdes_7series: refactor IOSERDES 2018-01-02 13:20:47 +01:00
Sebastien Bourdeauducq d5b5076f67 gateware/ad5360_monitor: fix SPI data decoding 2017-10-26 11:58:59 +08:00
Sebastien Bourdeauducq 412548a86c gateware: add AD5360 monitor (untested) 2017-10-23 20:09:28 +08:00
Sebastien Bourdeauducq 4fa823b62a gateware: add support for SPI-over-LVDS 2017-10-23 15:04:01 +08:00
Robert Jördens 3cbbcdfe96 sawg: don't enable_replace for Config 
closes #762
 2017-06-28 20:31:40 +02:00
Robert Jördens f4c6879c76 sawg: special case Config RTIO address 2017-06-22 10:26:29 +02:00
Sebastien Bourdeauducq 9ab63920e0 Remove Pipistrello support 
Closes #658
Closes #381
 2017-05-15 17:17:44 +08:00
Sebastien Bourdeauducq a7de58b604 rtio: Inout → InOut 2017-03-14 14:18:55 +08:00
Sebastien Bourdeauducq 86f6b391b7 ad9xxx -> ad9_dds 2017-01-04 11:34:52 +01:00
Robert Jördens 8381db279f sawg: wire up all HBF outputs, latency compensation in phys, simplify 2016-12-14 19:16:07 +01:00
Robert Jördens 1c84d1ee59 Merge branch 'master' into phaser2 
* master:
  rtio: support differential ttl
  RELEASE_NOTES: int(a, width=b) removal, use int32/64
  pc_rpc: use ProactorEventLoop on Windows (#627)
 2016-11-24 15:05:49 +01:00
Robert Jördens 95c885b580 rtio: support differential ttl 2016-11-24 15:04:12 +01:00
Robert Jördens 4160490e0a Merge branch 'phaser' into phaser2 
* phaser: (23 commits)
  RELEASE_NOTES: update
  pipistrello: add some inputs
  Remove last vestiges of nist_qc1.
  Fully drop AD9858 and kc705-nist_qc1 support (closes #576).
  coredevice.dds: reimplement fully in ARTIQ Python.
  compiler: unbreak casts to int32/int64.
  analyses.constness: fix false positive on x[...].
  inferencer: significantly improve the op-assignment diagnostic.
  Fix tests.
  Move mu_to_seconds, seconds_to_mu to Core.
  artiq_devtool: don't crash on invalid utf-8.
  artiq_devtool: detect a race condition during connect.
  llvm_ir_generator: handle no-op coercions.
  conda: use development version of migen/misoc
  Revert accidentally committed code.
  Revert "gateware: increase RTIO FIFO sizes for NIST_CLOCK. Closes #623"
  analyses.invariant_detection: implement (#622).
  Fix whitespace.
  coredevice.dds: work around the round(numpy.float64()) snafu.
  coredevice.dds: update from obsolete int(width=) syntax (fixes #621).
  ...
 2016-11-21 17:29:46 +01:00
Robert Jördens f7e8961ab0 Merge branch 'master' into phaser 
* master: (23 commits)
  RELEASE_NOTES: update
  pipistrello: add some inputs
  Remove last vestiges of nist_qc1.
  Fully drop AD9858 and kc705-nist_qc1 support (closes #576).
  coredevice.dds: reimplement fully in ARTIQ Python.
  compiler: unbreak casts to int32/int64.
  analyses.constness: fix false positive on x[...].
  inferencer: significantly improve the op-assignment diagnostic.
  Fix tests.
  Move mu_to_seconds, seconds_to_mu to Core.
  artiq_devtool: don't crash on invalid utf-8.
  artiq_devtool: detect a race condition during connect.
  llvm_ir_generator: handle no-op coercions.
  conda: use development version of migen/misoc
  Revert accidentally committed code.
  Revert "gateware: increase RTIO FIFO sizes for NIST_CLOCK. Closes #623"
  analyses.invariant_detection: implement (#622).
  Fix whitespace.
  coredevice.dds: work around the round(numpy.float64()) snafu.
  coredevice.dds: update from obsolete int(width=) syntax (fixes #621).
  ...
 2016-11-21 17:29:39 +01:00
whitequark 5e8888d5f3 Fully drop AD9858 and kc705-nist_qc1 support (closes #576). 2016-11-21 15:14:17 +00:00
Robert Jördens bcde26f990 Revert "phaser: cap phy data width to 64 temporarily" 
This reverts commit 342b9e977e.
 2016-11-18 17:08:44 +01:00
Robert Jördens 342b9e977e phaser: cap phy data width to 64 temporarily 2016-11-18 15:46:59 +01:00
Robert Jördens d678bb3fb6 phaser: update sawg tests 2016-11-18 15:23:56 +01:00
Robert Jördens ea0c304a0c phaser2: wip 2016-10-27 01:00:42 +02:00
Robert Jördens f5f7acc1f8 ttl_simple: add pure Input 
(no Tristate for internal signals)
 2016-10-10 17:13:23 +02:00
Robert Jördens 4a0eaf0f95 phaser: add jesd204b rtio dds 
gateware: add jesd204b awg

gateware: copy phaser (df3825a)
dsp/tools: update satadd mixin
phaser: no DDS stubs
dsp: accu fix
phaser: cleanup/reduce

sawg: kernel support and docs

sawg: coredevice api fixes

sawg: example ddb/experiment

phaser: add conda package

examples/phaser: typo

sawg: adapt tests, fix accu stb

sawg: tweak dds parameters

sawg: move/adapt/extend tests

sawg: test phy, refactor

phaser: non-rtio spi

phaser: target cli update

phaser: ad9154-fmc-ebz pins

phaser: reorganize fmc signal naming

phaser: add test mode stubs

phaser: txen is LVTTL

phaser: clk spi xfer test

phaser: spi for ad9154 and ad9516

phaser: spi tweaks

ad9154: add register map from ad9144.xml

ad9516: add register map from ad9517.xml and manual adaptation

ad9154_reg: just generate getter/setter macros as well

ad9154: reg WIP

ad9154: check and fix registers

kc705: single ended rtio_external_clk

use single ended user_sma_clk_n instead of p/n to free up one clock sma

kc705: mirror clk200 at user_sma_clock_p

ad9516_regs.h: fix B_COUNTER_MSB

phase: wire up clocking differently

needs patched misoc

kc705: feed rtio_external_clock directly

kc705: remove rtio_external_clk for phaser

phaser: spi tweaks

ad9516: some startup

ad9516_reg fixes

phaser: setup ad9516 for supposed 500 MHz operation

ad9516: use full duplex spi

ad9154_reg: add CONFIG_REG_2

ad9154_reg: fixes

phaser: write some ad9154 config

ad9154_reg: fixes

ad9154: more init, and human readable setup

ad9154/ad9516: merge spi support

ad9154: status readout

Revert "kc705: remove rtio_external_clk for phaser"

This reverts commit d500288bb44f2bf2eeb0c2f237aa207b0a8b1366.

Revert "kc705: feed rtio_external_clock directly"

This reverts commit 8dc7825519e3e75b7d3d29c9abf10fc6e3a8b4c5.

Revert "phase: wire up clocking differently"

This reverts commit ad9cc450ffa35abb54b0842d56f6cf6c53c6fbcc.

Revert "kc705: mirror clk200 at user_sma_clock_p"

This reverts commit 7f0dffdcdd28e648af84725682f82ec6e5642eba.

Revert "kc705: single ended rtio_external_clk"

This reverts commit a9426d983fbf5c1cb768da8f1da26d9b7335e9cf.

ad9516: 2000 MHz clock

phaser: test clock dist

phaser: test freqs

ad9154: iostandards

phaser: drop clock monitor

phaser: no separate i2c

phaser: drive rtio from refclk, wire up sysref

phaser: ttl channel for sync

ad9154: 4x interp, status, tweaks

phaser: sync/sysref 33V banks

phaser: sync/sysref LVDS_25 inputs are VCCO tolerant

phaser: user input-only ttls

phaser: rtio fully from refclk

ad9154: reg name usage fix

ad9154: check register modifications

Revert "ad9154: check register modifications"

This reverts commit 45121d90edf89f7bd8703503f9f317ad050f9564.

ad9154: fix status code

ad9154: addrinc, recal serdes pll

phaser: coredevice, example tweaks

sawg: missing import

sawg: type fixes

ad9514: move setup functions

ad9154: msb first also decreasing addr

phaser: use sys4x for rtio internal ref

phaser: move init code to main

phaser: naming cleanup

phaser: cleanup pins

phaser: move spi to kernel cpu

phaser: kernel support for ad9154 spi

ad9154: add r/w methods

ad9154: need return annotations

ad9154: r/w methods are kernels

ad9154_reg: portable helpers

phaser: cleanup startup kernel

ad9154: status test

ad9154: prbs test

ad9154: move setup, document

phaser: more documentation
 2016-10-05 16:17:50 +02:00
Robert Jördens a91ed8394c rtio: add input-only channel 2016-10-05 16:17:50 +02:00
Robert Jördens 279f0d568d rtio: support differential ttl 2016-10-05 16:17:50 +02:00
Sebastien Bourdeauducq a7dd356d30 rtio/phy/ttl: support 'set sensitivity and sample' command (#218) 2016-09-07 15:42:09 +08:00
Sebastien Bourdeauducq 7a2405146a rtio: do not reset DDS and SPI PHYs on RTIO reset (#503) 2016-07-09 10:07:19 +08:00
Sebastien Bourdeauducq 542a375305 rtio: remove NOP suppression capability 
Back when RTIO was driving TTLs, this functionality made it simpler to use by removing some irrelevant underflows.

The same technique is not applicable to DDS and SPI, so the user will have to deal with such underflows.

This patch makes the behavior of RTIO more consistent and the code simpler.
 2016-03-10 09:47:29 +08:00
Sebastien Bourdeauducq 2e39802a61 rtio/wishbone: make replace configurable 2016-03-10 09:44:05 +08:00
Sebastien Bourdeauducq 03b53c3af9 rtio: disable replace on rt2wb channels 2016-03-09 23:37:04 +08:00
Robert Jördens a0083f4501 Revert "gateware/rt2wb: only input when active" 
This reverts commit 1b08e65fa1.
 2016-02-29 16:44:11 +01:00
Robert Jördens cb8815cc65 Revert "gateware/rt2wb: support combinatorial ack" 
This reverts commit f73228f248.
 2016-02-29 16:44:04 +01:00
Robert Jördens f73228f248 gateware/rt2wb: support combinatorial ack 2016-02-29 15:40:55 +01:00
Robert Jördens 1b08e65fa1 gateware/rt2wb: only input when active 2016-02-29 14:56:29 +01:00
Robert Jördens f8732acece rtio.spi: drop unused argument 2016-02-28 21:06:20 +01:00
Robert Jördens e7146cc999 gateware.spi: design sketch 2016-02-26 17:03:08 +01:00
Sebastien Bourdeauducq e26147b2ac gateware,runtime: use new migen/misoc 2015-11-04 00:35:03 +08:00
Sebastien Bourdeauducq e46ba83513 rtio/dds: use rio_phy domain to reset FTW tracker. Closes #120 2015-10-04 22:53:51 +08:00
Robert Jördens 01416bb0be copyright: claim contributions 
These are contributions of >= 30% or >= 20 lines (half-automated).

I hereby resubmit all my previous contributions to the ARTIQ project
under the following terms:

    This program is free software: you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation, either version 3 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program.  If not, see <http://www.gnu.org/licenses/>.

Closes #130

Signed-off-by: Robert Jordens <jordens@gmail.com>
 2015-09-06 16:08:57 -06:00
Sebastien Bourdeauducq 90ce54d8d5 gateware/dds/monitor: support onehot selection, strip reset 2015-08-27 15:54:01 +08:00
Robert Jördens fb339d294e serdes_s6: no need to reset 2015-07-28 12:54:31 -06:00
Robert Jördens 9ac5bc52d4 rtio: add spartan6 serdes, 4x and 8x 2015-07-27 21:01:15 -06:00
Sebastien Bourdeauducq 5b50f5fe05 rtio/ttl_serdes_7series: use recommended OSERDES T configuration 2015-07-27 10:50:50 +08:00
Sebastien Bourdeauducq 940aa815dd rtio/ttl_serdes: cleanup/rewrite 2015-07-27 01:44:52 +08:00
Yann Sionneau d90dff4ef1 rtio: add SERDES TTL (WIP) 2015-07-26 17:40:34 +08:00
Robert Jördens 47191eda91 dds monitor: relax timing (for pipistrello) 2015-07-19 21:36:51 -06:00
Sebastien Bourdeauducq 58c0150822 ttl: improve clockgen doc 2015-07-05 19:07:13 +02:00
Sebastien Bourdeauducq 753d61b38f complete support for TTL clock generator 2015-07-04 18:36:01 +02:00
Sebastien Bourdeauducq 2881d5f00a gateware: add RTIO clock generator 2015-07-02 18:20:26 +02:00
Sebastien Bourdeauducq 944bfafefa soc: support QC2 and AD9914 (untested) 2015-06-28 21:37:27 +02:00
Sebastien Bourdeauducq f47c2e54e1 DDS monitor fixes 2015-06-19 17:36:46 -06:00
Sebastien Bourdeauducq 5a9bdb2e33 DDS monitoring 2015-06-19 15:30:17 -06:00
Sebastien Bourdeauducq b2af0f6cc3 soc,runtime: support TTL override 2015-06-09 19:51:02 +08:00
Sebastien Bourdeauducq b81151eb42 soc: rtio monitor 2015-06-02 17:41:40 +08:00
Sebastien Bourdeauducq a36c51eb83 DDS over RTIO (batch mode not supported yet) 2015-05-08 14:44:39 +08:00
Sebastien Bourdeauducq cb65b1e322 rtio/phy/ttl_simple: reset sensitivity with RTIO logic 2015-05-02 16:17:31 +08:00
Sebastien Bourdeauducq a61d701d47 rtio: decouple PHY reset from logic reset 2015-05-02 11:47:11 +08:00
Sebastien Bourdeauducq 71167b8adf rtio: do not attempt latency compensation in gateware 2015-04-16 13:09:29 +08:00
Sebastien Bourdeauducq 30dffb6644 rtio/phy: add wishbone adapter 2015-04-15 20:39:40 +08:00
Sebastien Bourdeauducq 4c10182c9f rtio: refactor, use rtlink 2015-04-14 19:44:45 +08:00