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Commit Graph

6850 Commits

Author SHA1 Message Date
whitequark
3b661b2b65 Fix environment corruption by ExceptHandler without a name. 2015-07-17 16:04:46 +03:00
39c6bc940c coreconfig: use new database API (closes #75) 2015-07-17 10:49:55 +02:00
9649e1837a gui: basic plotting 2015-07-16 20:52:53 +02:00
a83473a19a sync_struct: clarify notify_cb doc 2015-07-16 20:52:27 +02:00
Yann Sionneau
78ee4bdb99 pyqtgraph: use more up to date revision a6d5e28 on develop branch 2015-07-16 20:00:08 +02:00
whitequark
2dcb744519 Fix inference for default arguments. 2015-07-16 17:26:31 +03:00
whitequark
f8e51e07d5 Add zero/one accessors to TBool, TInt, TFloat. 2015-07-16 16:03:24 +03:00
whitequark
bcd1832203 Ensure bindings are created in correct order for e.g. "x, y = y, x". 2015-07-16 15:59:59 +03:00
whitequark
5756cfcebc Correctly infer type of list(iterable). 2015-07-16 15:35:46 +03:00
whitequark
6cda67c0c6 Ensure type comparisons see through type variables. 2015-07-16 14:59:05 +03:00
whitequark
c1e7a82e97 Add IndexError and ValueError builtins. 2015-07-16 14:58:40 +03:00
whitequark
b58fa9067d Add attributes to TRange.
Also make attributes an OrderedDict, for stable order during
LLVM IR generation.
2015-07-16 14:57:44 +03:00
whitequark
a6950bf11d Move builtin.is_{builtin,exn_constructor} to types. 2015-07-16 14:56:39 +03:00
whitequark
5000f87dfc Rename the field of CoerceT from expr to value. 2015-07-16 14:55:23 +03:00
whitequark
e9416f4707 Convert Slice into typed SliceT. 2015-07-16 14:54:04 +03:00
whitequark
53fb03d1bf Restrict comprehensions to single for and no if clauses. 2015-07-16 14:52:41 +03:00
whitequark
227f97f8a3 Add inference for Index, Slice and ExtSlice. 2015-07-16 04:22:41 +03:00
66940ea815 rtio: disable NOP suppression after reset and underflow 2015-07-15 20:54:55 +02:00
Yann Sionneau
08eec40861 manual: building LLVM as shared libraries is not recommended on Linux and not supported on Windows 2015-07-15 17:34:06 +02:00
Yann Sionneau
774c66a209 manual: also build LLVM native target (needed for py2llvm test) 2015-07-15 17:32:32 +02:00
Yann Sionneau
fa4f38b871 manual: add missing llvmlite patches 2015-07-15 17:31:57 +02:00
Yann Sionneau
511d51977e llvmlite: split patch to be cleaner. close #72 2015-07-15 17:28:05 +02:00
Yann Sionneau
af20efafa5 conda: update llvmlite-or1k package and up the build number 2015-07-15 17:28:05 +02:00
f836465585 coredevice: environment -> runtime 2015-07-15 11:20:41 +02:00
84de2fb28b expid: experiment -> class_name 2015-07-15 11:08:12 +02:00
255aba9247 test/worker: remove stale handler 2015-07-15 11:07:48 +02:00
7de56666e3 worker,environment: support scanning of arguments with no default 2015-07-15 10:59:48 +02:00
9ed4dcd7d1 repository: load experiments in worker, list arguments 2015-07-15 10:54:44 +02:00
whitequark
c724e024ce Fix inference for multiple-target assignments. 2015-07-15 06:33:44 +03:00
7770ab64f2 worker: factor timeouts 2015-07-14 23:43:08 +02:00
whitequark
9ff9f85f19 Add accessors to instructions. 2015-07-14 22:18:38 +03:00
a07f2473b0 manual: add core device moninj port 2015-07-14 20:06:29 +02:00
e20b260117 gui: fix selections 2015-07-14 19:08:08 +02:00
21e8596d8c gui: RT results overview 2015-07-14 17:31:18 +02:00
55cd41444e gui/DictSync: better support of nested structs 2015-07-14 17:30:55 +02:00
1edeb5a13f sync_struct: docstring cleanup 2015-07-14 17:30:21 +02:00
84e7f55df3 gui: fix DDS class recognition 2015-07-14 17:28:26 +02:00
Yann Sionneau
6e3fd591f7 gui: remove unnecessary QSplitter 2015-07-14 16:59:04 +02:00
whitequark
bdcb24108b Add basic IR generator. 2015-07-14 08:56:51 +03:00
whitequark
f417ef31a4 Make binop coercion look through CoerceT nodes.
This fixes inference for "x = 1 + 1" after int monomorphization.
2015-07-14 06:42:09 +03:00
Yann Sionneau
90ba9f7bbf llvmlite: rename our package to be llvmlite_or1k to avoid collision with llvmlite package needed for numba 2015-07-14 01:01:56 +02:00
56fc7a484c TTLInOut: timestamp -> timestamp_mu 2015-07-13 23:21:29 +02:00
820ff2da2c test/coredevice: WA for lack of constant string support in compiler (see issue #68) 2015-07-13 22:22:26 +02:00
32d141f5ac refactor ddb/pdb/rdb 2015-07-13 22:21:32 +02:00
whitequark
ebe243f8d9 Add printing of SSA functions. 2015-07-13 21:08:20 +03:00
whitequark
dbdd45acc5 Add missing return. 2015-07-13 20:52:55 +03:00
whitequark
7c9afcce85 Fix Python default argument fiasco. 2015-07-13 20:52:48 +03:00
8b02b58a77 sync_struct/Notifier: do not pass root param to publish 2015-07-13 17:12:59 +02:00
0e92cfe053 artiq_run: remove support for stale watchdog API 2015-07-11 22:26:37 +02:00
whitequark
7c52910dc5 Add a basic SSA IR. 2015-07-11 18:46:37 +03:00