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artiq
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4 Commits

Author SHA1 Message Date
Spaqin 17efc28dbe
DRTIO: RTIO/SYS clock merge 2022-12-17 15:39:54 +08:00
occheung 09945ecc4d gateware: fix drtio/dma tests 2021-11-08 16:59:08 +08:00
Sebastien Bourdeauducq 87e0384e97 drtio: separate aux controller 
This helps with managing CSR groups and heterogeneous (satellite/repeaters) DRTIO cores.
 2018-09-05 17:56:58 +08:00
Sebastien Bourdeauducq 657afd770e artiq/test/gateware -> artiq/gateware/test 
This allows gateware simulations to be skipped or not considered for coverage when using test discovery.
 2017-01-30 09:00:55 +08:00