M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 1
Code Issues Projects Releases Wiki Activity
8,838 Commits 13 Branches 35 Tags 26 MiB
Commit Graph

993 Commits

Author SHA1 Message Date
Marius Weber f97baa8aec phaser: workaround malformed output with `mixer_ena=1` & `nco_ena=0` 
When Phaser is powered on and `init()` is first called, enabling the
DAC-mixer while leaving the NCO disabled causes malformed output.
This commit implements a workaround by making sure the NCO is enabled,
before being set to the disired state.

This commit also avoids the following procedure, resulting in
malformed output:
1. Operate Phaser with the DAC Mixer and NCO enabled
2. Set the NCO to a non-zero frequency
3. Disable the NCO in the device_db
4. Re-initialise Phaser

After this procedure, with CMIX disabled, incorrect output is produced.
To clear the fault one must re-enable the NCO and write the NCO freqeuncy
to zero before disabling the NCO.

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>
 2021-05-08 14:48:47 +01:00
Marius Weber 4fa2028671 phaser: fix coarse mixer register offset 
The CMIX bits are bits 12-15 in register 0x0d. This has been checked
against the datasheet and verified on hardware. Until now, the bit for
CMIX1 was written to CMIX0. The CMIX0 bit was written to a reserved bit.

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>
 2021-05-08 14:48:47 +01:00
Marius Weber 515cfa7dfb Phaser: expose coarse mixer and document need to enable the DAC-mixer. 
in some use cases a larger tunable range than available via the DUC may
be needed. Some use cases may wish to combine the coarse mixer with the
DUC to extend the tunable range.

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>
 2021-05-08 14:48:47 +01:00
Marius Weber 4f812cc4ed Phaser: zero oscillator amplitude after `init()` (close #1651) 
Currently, `init()` leaves a single oscillator at full scale. The phase
accumulator of this oscillator is held continuously cleared. Provided no
upconverting mechanism is active (DUC, CMIX, NCO), this produces a full-scale
DC voltage. The DC voltage is blocked by hardware capacitors. This behaviour
is not mentioned by the `init` documentation.

If one attempts to use any other oscillator without reducing the amplitude
of the oscillator enabled by `init`, there is by significant clipping.

In the case that the NCO or CMIX are configured via the device_db
(suggested in the docs), leaving the osillator at full scale results in
full RF output power after calling `init()`. This may plausibly damage loads
driven by phaser.

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>
 2021-05-08 14:48:47 +01:00
Marius Weber 407fba232d Phaser upconverter: set phase-frequency detector to 62.5 MHz (close #1648) 
The suitable PFD clock depends on the use case and will likely need
to be configured by some users. All things being equal, a higher PFD
clock is desirable as is results in lower local oscillator phase-noise.

Phaser was designed around a maximum PFD clock of 62.5 MHz. In integer mode,
with no local oscillator frequency divisor set, a 62.5 MHz PFD clock results
in a 125 MHz local oscillator step size. Given the +-200 MHz range of the DUC
(more if using the DAC mixer), this step size will be acceptable to many.
This seems like the most appropreate default configuration as it should offer
the best phase-noise performance.

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>
 2021-05-08 14:48:47 +01:00
Marius Weber 75445fe5f0 Phaser: expose and automate clearing of DAC `sif_sync` (close #1630 and #1650) 
`sif_sync` must be triggered to apply NCO frequency changes. To achieve per
channel frequency tunability exeeding the range of the DUC, the NCO frequeny must
adjusted. User code will need to trigger `sif_sync` to achieve this.

`sif_sync` can only be triggered if the bit was cleared. To avoid this pitfall,
the clearing of `sif_sync` is automated.

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>
 2021-05-08 14:48:47 +01:00
Marius Weber 1c96797de5 Phaser upconverter: Follow datasheet procedure for VCO calibration (close #1643) 
Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>
 2021-05-08 14:48:47 +01:00
Marius Weber 7404152e4c Phaser upconverter: rename `ndiv` -> `nint` to match datasheet (close #1638) 
Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>
 2021-05-08 14:48:47 +01:00
Marius Weber eb477ee06b phaser: print gw_rev in debug mode 2021-05-08 14:48:46 +01:00
Marius Weber c7e992e26d Phaser: flake8 
Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>
 2021-05-08 14:48:46 +01:00
Sebastien Bourdeauducq eb38b664e3 phaser: typo 2021-05-07 10:00:10 +08:00
Peter Drmota 47bf5d36af coredevice.comm_kernel: Fix unpacking of lists of numpy.int64 
test.coredevice.test_embedding: Add tests for list of numpy.int64
 2021-04-21 15:46:58 +01:00
Leon Riesebos 2671c271d4 ad99xx unified type annotations for cfg_sw() methods and fixed test cases 
closes #1642

Signed-off-by: Leon Riesebos <leon.riesebos@duke.edu>
 2021-04-21 11:29:55 +08:00
Leon Riesebos d745d50245 ad99xx added additional kernel invariants 
Signed-off-by: Leon Riesebos <leon.riesebos@duke.edu>
 2021-04-21 11:18:31 +08:00
Leon Riesebos 4a6201c083 ad99xx make kernel invariants instance variable 
prevents mutations on class variable that applies to all instances at once
closes #1654

Signed-off-by: Leon Riesebos <leon.riesebos@duke.edu>
 2021-04-21 11:18:31 +08:00
Robert Jördens ffe1c9f9b1
Merge pull request #1628 from pathfinder49/fastino_mu_fix 
fastino: ensure `xxx_to_mu()` methods return int32 on the host
 2021-04-15 15:02:12 +02:00
Marius Weber bda5aa7c7e fastino: ensure `xxx_to_mu()` methods return int32 on the host 
Currently running `voltage_to_mu()` or `voltage_group_to_mu()` on the host will
convert all machine unit values to int64. This leads to issues when machine units
are returned from RPCs.

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>
 2021-04-15 11:41:22 +01:00
Harry Ho fc59791583 jsonschema: mirny: fix clk_sel default value 2021-03-30 16:06:56 +08:00
Harry Ho 8002fcf8bb jsonschema: style 2021-03-29 17:49:43 +08:00
Harry Ho 5f32cb7196 jsonschema: mirny: accept string enums for validating clk_sel 2021-03-29 17:49:43 +08:00
David Nadlinger 888696f588 coredevice: Fix RPC typing for bool lists/arrays 
GitHub: Fixes #1635.
 2021-03-20 00:03:10 +00:00
Leon Riesebos d04bcd8754 add get_*() functions to ad9910, ad9912, and urukul. closes #1616 
Signed-off-by: Leon Riesebos <leon.riesebos@duke.edu>
 2021-03-15 13:06:24 +08:00
Leon Riesebos c22f731a61 added typing and reformatted driver for ad9910, ad9912, and urukul 
Signed-off-by: Leon Riesebos <leon.riesebos@duke.edu>
 2021-03-15 13:06:24 +08:00
Astro 3844cde97b jsonschema: validate hw_dev depending on target 2021-02-12 11:09:01 +08:00
Astro 4b2ed67dd7 coredevice_generic.schema.json: add "min_artiq_version" 2021-02-10 15:26:15 +08:00
Sebastien Bourdeauducq 1213f78ee9 jsonschema: support kasli_soc 2021-02-07 13:39:01 +08:00
Robert Jördens 2f5ea67b69
Merge pull request #1596 from airwoodix/fix-adf5356-init 
coredevice/adf5356: fix initial device detection
 2021-02-02 18:20:08 +01:00
Etienne Wodey d691b05d78 coredevice/mirny: better error handling for clk_sel 
Signed-off-by: Etienne Wodey <wodey@iqo.uni-hannover.de>
 2021-02-02 16:23:47 +01:00
Etienne Wodey 6f8e788620 coredevice/mirny: support human readable clk_sel 
In init(), read hw_rev to derive clk_sel code from user string.

Signed-off-by: Etienne Wodey <wodey@iqo.uni-hannover.de>
 2021-01-29 18:46:47 +01:00
Etienne Wodey a8bc98a77b coredevice/adf5356: fix initial device detection 
Signed-off-by: Etienne Wodey <wodey@iqo.uni-hannover.de>
 2021-01-28 18:29:40 +01:00
David Nadlinger f9872bb7b8 coredevice: Handle prematurely closed sockets in comm_kernel receive loop 
recv() returns 0 instead of data if the socket has already
been closed. This is translated into a zero-length list on
the Python layer. Previously, the code would enter an
infinite loop if the socket was closed while attempting
to receive data.
 2021-01-26 18:10:49 +08:00
David Nadlinger f1fd42ea98 coredevice: Re-enable TCP keepalive 
This partially reverts commit b5e1bd3fa2,
which had removed keepalive. This, however, led to experiments
hanging forever if the core device had dropped the connection
(e.g. to a kernel CPU panic, or the device being rebooted).

The chosen keepalive settings are fairly conservative (with the
10 s timeout) to avoid any possible interaction with smoltcp's
3 s ARP try interval (see GitHub issue #1150), even though this
should be a non-issue now due to the larger ARP cache.
 2021-01-26 18:10:49 +08:00
pca006132 8148fdb8a7
use device endian for core device protocols (#1591) 2021-01-22 16:33:21 +08:00
David Nadlinger 1e443a3aea coredevice: Reuse Target.little_endian for protocol endianness [nfc] 2021-01-21 09:11:54 +01:00
pca006132 ec72eeda46 coredevice: use device endian for kernel and RPC 2021-01-21 09:07:48 +01:00
Robert Jördens 261870bdee phaser: fix oscillator rtio address for even base addresses 
close #1580
 2021-01-19 16:56:50 +01:00
Sebastien Bourdeauducq c675488a99 reorganize JSON schema files 2021-01-16 10:43:14 +08:00
Sebastien Bourdeauducq 1ce505c547 coredevice: remove obsolete watchdog code (#1458) 2020-12-08 13:25:39 +08:00
Marius Weber 3e38833020 ad9910: fix `turns_to_pow` return-type on host 
When run on the host, the `turns_to_pow` retrun-type is numpy.int64.
Sensibly, the compiler does not attempt to convert `numpy.int64` to `int32`.

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>
 2020-11-13 18:54:47 +01:00
David Nadlinger 292043a0a7 compiler: Raise AssertionErrors instead of abort()ing on all targets 2020-11-10 20:40:18 +01:00
Etienne Wodey dbcac62fd0 coredevice: adf5356: fix/adjust docs 
Signed-off-by: Etienne Wodey <wodey@iqo.uni-hannover.de>
 2020-11-10 10:49:22 +08:00
Etienne Wodey 3844123c13 coredevice: adf5356: add enable/disable and power setting for outA 
Signed-off-by: Etienne Wodey <wodey@iqo.uni-hannover.de>
 2020-11-10 10:49:22 +08:00
Etienne Wodey b200465cce coredevice: adf5355: rename to adf5356 
Signed-off-by: Etienne Wodey <wodey@iqo.uni-hannover.de>
 2020-11-10 10:49:22 +08:00
Etienne Wodey d433f6e86d coredevice: adf5355: more general PLL parameters calculation 
Signed-off-by: Etienne Wodey <wodey@iqo.uni-hannover.de>
 2020-11-10 10:49:22 +08:00
Etienne Wodey b856df7c35 coredevice: adf5355: cleanup, style 2020-11-10 10:49:22 +08:00
Etienne Wodey 211500089f coredevice: mirny/adf5355: add basic high-level interface 
Signed-off-by: Etienne Wodey <wodey@iqo.uni-hannover.de>
 2020-11-10 10:49:22 +08:00
David Nadlinger 4f311e7448 compiler: Raise exception on failed assert()s rather than panic 
This allows assert() to be used on Zynq, where abort() is not
currently implemented for kernels. Furthermore, this is arguably
the more natural implementation of assertions on all kernel targets
(i.e. where embedding into host Python is used), as it matches host
Python behavior, and the exception information actually makes it to
the user rather than leading to a ConnectionClosed error.

Since this does not implement printing of the subexpressions, I
left the old print+abort implementation as default for the time
being.

The lit/integration/instance.py diff isn't just a spurious change;
the exception-based assert implementation exposes a limitation in
the existing closure lifetime tracking algorithm (which is not
supposed to be what is tested there).

GitHub: Fixes #1539.
 2020-11-10 00:51:24 +01:00
Etienne Wodey ecef5661ce coredevice/phaser: fix typos in docstring 
Signed-off-by: Etienne Wodey <wodey@iqo.uni-hannover.de>
 2020-10-29 20:27:08 +01:00
Robert Jördens eecd97ce4c phaser: debug and comments 2020-09-27 17:15:16 +00:00
Robert Jördens c453c24fb0 phaser: tweak slacks 2020-09-26 21:16:08 +00:00
Robert Jördens 6c8bddcf8d phaser: tune sync_dly 2020-09-26 21:13:00 +00:00
Robert Jördens 569e5e56cd phaser: autotune and fix fifo_offset 2020-09-26 20:37:16 +00:00
Robert Jördens 2fba3cfc78 phaser: debug init, systematic bring-up 2020-09-25 20:54:59 +00:00
Robert Jördens fec2f8b763 phaser: increase slack for iotest 2020-09-24 10:59:22 +00:00
Robert Jördens 6e6480ec21 phaser: tweak slacks and errors, identify trf 2020-09-24 08:38:30 +00:00
Robert Jördens 03d5f985f8 phaser: another artiq-python signed integer quirk 2020-09-23 15:40:54 +00:00
Robert Jördens ef65ee18bd dac34h84: unflip spectrum, clear nco 2020-09-23 08:35:56 +00:00
Robert Jördens 50b4eb4840 Merge branch 'master' into phaser 
* master: (26 commits)
  fastino: documentation and eem pass-through
  kasli2: forward sma_clkin to si5324
  test: relax test_dma_playback_time on Zynq
  rpc: fixed _write_bool
  fastino: document/cleanup
  build_soc: remove assertion that was used for test runs
  metlino_sayma_ttl: Fix RTIO frequency & demo code (#1516)
  Revert "test: temporarily disable test_async_throughput"
  build_soc: rename identifier_str to gateware_identifier_str
  test: relax loopback gate timing
  test: temporarily disable test_async_throughput
  test: relax test_pulse_rate on Zynq
  test: skip NonexistentI2CBus if I2C is not supported
  build_soc: override identifier_str only for gateware
  examples: add Metlino master, Sayma satellite with TTLOuts via FMC
  sayma_amc: add support for 4x DIO output channels via FMC
  fmcdio_vhdci_eem: fix pin naming
  build_soc: add identifier_str override option
  RPC: optimization by caching
  test: improved test_performance
  ...
 2020-09-22 16:02:25 +00:00
Robert Jördens c55f2222dc fastino: documentation and eem pass-through 
* Repeat information about matching log2_width a few times
  in the hope that people read it. #1518
* Pass through log2_width in kasli_generic json. close #1481
* Check DAC value range. #1518
 2020-09-22 17:58:53 +02:00
Robert Jördens 85d16e3e5f phaser: tweaks 2020-09-22 15:27:38 +00:00
Robert Jördens fd5e221898 phaser: dac and trf register maps, init code 2020-09-22 14:08:39 +00:00
Robert Jördens 3e036e365a phaser: nco, settings and init tweaks 2020-09-22 09:52:49 +00:00
Robert Jördens fdb2867757 phaser: fewer iotest patterns 2020-09-21 17:06:26 +02:00
Robert Jördens d730851397 phaser: elaborate init sequence, more tests 2020-09-21 15:05:29 +00:00
Robert Jördens f0959fb871 phaser: iotest early, check_alarms 2020-09-17 14:13:58 +00:00
Robert Jördens b15e388b5f ad53xx: distinguish errors 2020-09-17 14:13:10 +00:00
Robert Jördens c18f515bf9 phaser: rework rtio channels, sync_dly, init() 2020-09-16 12:23:07 +00:00
Robert Jördens f3b0398720 phaser: n=2, m=16, sync_dly 2020-09-16 09:19:15 +00:00
Robert Jördens 9b58b712a6 phaser: doc tweaks 2020-09-15 12:35:26 +00:00
Robert Jördens ff57813a9c phaser: init [wip] 2020-09-15 08:46:47 +00:00
Robert Jördens 07418258ae phaser: init [wip] 2020-09-15 08:46:10 +00:00
Robert Jördens 3a79ef740b phaser: work around integer size 2020-09-15 08:46:10 +00:00
Robert Jördens b449e7202b phaser: rework docs 2020-09-15 08:46:10 +00:00
Robert Jördens b619f657b9 phaser: doc tweaks 2020-09-12 19:59:49 +02:00
Robert Jördens c3728678d6 phaser: document, elaborate comments, some fixes 2020-09-12 17:35:14 +00:00
Robert Jördens e505dfed5b phaser: refactor coredevice driver 2020-09-12 14:17:40 +00:00
Robert Jördens fdd2d6f2fb phaser: SI methods 2020-09-12 11:02:37 +00:00
Robert Jördens e69bb0aeb3 phaser: add comment about get_dac_data 2020-09-07 16:06:16 +00:00
pca006132 6195b1d3a0 rpc: fixed _write_bool 
Closes #1519
 2020-09-04 13:49:22 +08:00
Robert Jördens 56aa22caeb fastino: document/cleanup 
* added documentation on `update`/`hold` mechanism
* mask machine unit values
* cleanup coredevice driver

close #1518
 2020-09-03 17:44:26 +02:00
Robert Jördens 272dc5d36a phaser: documentation 2020-08-28 16:36:44 +00:00
pca006132 b2572003ac RPC: optimization by caching 
This reduced the calls needed for socket send/recv.
 2020-08-28 14:58:34 +08:00
Sebastien Bourdeauducq 7cf974a6a7 comm_kernel: fix typo 2020-08-28 12:25:23 +08:00
Robert Jördens 68bfa04abb phaser: trf readback strobe spi changes 2020-08-27 15:31:42 +00:00
Robert Jördens c10ac2c92a phaser: add trf, duc, interfaces, redo body assembly, use more natrual iq ordering (i lsb) 2020-08-27 14:26:09 +00:00
Robert Jördens e5e2392240 phaser: wire up multidds 2020-08-26 17:12:41 +00:00
Robert Jördens d1be1212ab phaser: coredevice shim, dds [wip] 2020-08-26 15:10:50 +00:00
pca006132 7181ff66a6 compiler: improved rpc performance for list and array 
1. Removed duplicated tags before each elements.
2. Use numpy functions to speedup parsing.
 2020-08-26 14:17:06 +08:00
Robert Jördens 20fcfd95e9 phaser: coredevice shim, readback fix 2020-08-24 15:46:31 +00:00
David Nadlinger 8783ba2072 compiler/firmware: RPCs for ndarrays 2020-08-09 17:08:43 +01:00
David Nadlinger 9af6e5747d compiler: Factor rpc_tag() out of llvm_ir_generator 2020-08-09 03:54:41 +01:00
pmldrmota 1df62862cd
AD9910: Write correct number of bits to POW register (#1498) 
* coredevice.ad9910: Add return type hints to conversion functions

* coredevice.ad9910: Make set_pow write correct number of bits
The AD9910 expects 16 bits. Thus, if writing 32 bits to the POW register, the chip would likely enter a locked-up state.

* coredevice.ad9910: Correct data alignment in write_16

Co-authored-by: Robert Jördens <rj@quartiq.de>

* coredevice.ad9910: Add function to read from 16 bit registers

Co-authored-by: drmota <peter.drmota@physics.ox.ac.uk>
Co-authored-by: Robert Jördens <rj@quartiq.de>
 2020-08-07 10:10:44 +02:00
Sebastien Bourdeauducq 2a2f5c4d58 comm_analyzer: make header error flag more general 2020-07-20 19:39:19 +08:00
charlesbaynham 2429a266f6
ad9912: Fix typing problem on ad9912 (#1466) 
Closes #1463

FTW and phase word were ambiguously typed, resulting in failure to compile
 2020-06-16 20:17:22 +02:00
Robert Jördens 9822b88d9b
ad9910: fix asf range (#1450) 
* ad9910: fix asf range

The ASF is a 14-bit word. The highest possible value is 0x3fff, not
0x3ffe. `int(round(1.0 * 0x3fff)) == 0x3fff`.

I don't remember and understand why this was 0x3ffe since the beginning.
0x3fff was already used as a default in `set_mu()`

Signed-off-by: Robert Jördens <rj@quartiq.de>

* RELEASE_NOTES: ad9910 asf scale change

Co-authored-by: David Nadlinger <code@klickverbot.at>
 2020-05-29 11:13:26 +02:00
Marius Weber 2538840756
Coredevice Input Validation (#1447) 
* Input validation and masking of SI -> mu conversions (close #1446)

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>

* Update RELEASE_NOTES

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>

Co-authored-by: Robert Jördens <rj@quartiq.de>
 2020-05-17 15:09:11 +02:00
Marius Weber b3b6cb8efe
ad53xx improvements (#1445) 
* ad53xx: voltage_to_mu() validation & documentation (closes #1443, #1444)
The voltage input (float) is checked for validity. If we need more
speed, we may want to check the DAC-code for over/underflow instead.

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>

* ad53xx documentation: voltage_to_mu is only valid for 16-bit DACs

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>

* AD53xx: add voltage_to_mu method (closes #1341)

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>

* ad53xx: improve voltage_to_mu performance
Interger comparison is faster than floating point math.

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>

* AD53xx: voltage_to_mu method now uses attribute values

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>

* Fixup RELEASE_NOTES.rst

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>

* ad53xx: documentation improvements

voltage_to_mu return value
14-bit DAC support

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>
 2020-05-08 19:23:43 +02:00
Sebastien Bourdeauducq e8b73876ab comm_kernel: add Zynq runtime identifier 2020-04-12 17:25:14 +08:00
Sebastien Bourdeauducq de57039e6e comm_kernel: cleanup 2020-04-12 16:02:36 +08:00
Sebastien Bourdeauducq 9dc24f255e comm_kernel: remove dead code 2020-04-12 15:06:46 +08:00
Robert Jördens e803830b3b fastino: support wide RTIO interface and channel groups 2020-03-05 17:55:04 +00:00
Sebastien Bourdeauducq 8451e58fbe ad9912: fix ftw width docstring 2020-02-27 02:11:12 +08:00
Robert Jördens 248230a89e fastino: style 2020-01-20 13:25:00 +01:00
Robert Jördens c45a872cba fastino: fix init, set_cfg 2020-01-20 13:25:00 +01:00
Robert Jördens 2c4e5bfee4 fastino: add [WIP] 2020-01-20 13:25:00 +01:00
Sebastien Bourdeauducq e427aaaa66 basemod_att: fix imports 2020-01-20 20:14:24 +08:00
Robert Jördens 7ab0282234 adf5355: style 2020-01-20 13:13:08 +01:00
Robert Jördens 9368c26d1c mirny: add to manual 2020-01-20 13:13:08 +01:00
Robert Jördens 01a6e77d89 mirny: add 
* This targets unrelease CPLD gateware (https://github.com/quartiq/mirny/issues/1)
* includes initial coredevice driver, eem shims, and kasli_generic tooling
* addresses the ARTIQ side of #1130
* Register abstraction to be written

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2020-01-20 13:13:08 +01:00
Sebastien Bourdeauducq 833f428391 sayma: fix hmc542 to/from mu 2020-01-16 09:10:32 +08:00
David Nadlinger 1e864b7e2d coredevice/suservo: Add separate methods for setting only the IIR offset 2019-12-30 20:02:22 +00:00
Sebastien Bourdeauducq b5e1bd3fa2 coredevice: simplify/cleanup network connection code 
This removes:
* host-side keepalive, which turns out not to be required
* custom connection timeout (the default is OK)
* SSH tunneling support (doesn't seem to be actually used anywhere)
 2019-12-23 19:53:49 +08:00
David Nadlinger af31c6ea21 coredevice: Don't use `is` to compare with integer literal 
This works on CPython, but is not guaranteed to do so, and
produces a warning since 3.8 (see https://bugs.python.org/issue34850).
 2019-12-22 05:46:41 +00:00
Sebastien Bourdeauducq fb2076a026 basemod_att: add dB functions, document 2019-12-21 14:56:41 +08:00
Sebastien Bourdeauducq d4e039cede basemod: add coredevice driver 2019-12-21 14:18:10 +08:00
Sebastien Bourdeauducq 8759c8d360 shiftreg: fix get method 2019-12-21 14:17:22 +08:00
Sebastien Bourdeauducq cab8c8249e coredevice/shiftreg: add get method 2019-12-20 18:58:50 +08:00
gthickman 56d4b70e01 ad9910 osk (#1387) 
* updated adoo10.py for RAM mode frequency control

* updated docstrings for set_cfr1() in ad9910.py

* fixed typo in ad9910.py

* added docstrings to ad9910.py

* removed OSK-related changes in AD9910, to be included in a separate branch.

* updated AD9910 set_cfr1 for control of OSK mode parameters

* updated AD9910 set_cfr1() for control of OSK mode parameters.
 2019-11-18 15:57:26 +01:00
Fabian Schmid f73e2a3d30 doc: clarify urukul attenuator behavior 
Closes #1386

Signed-off-by: Fabian Schmid <fabian.schmid@mpq.mpg.de>
 2019-11-18 15:56:00 +01:00
Garrett f8a7e278b8 removed OSK-related changes in AD9910, to be included in a separate branch. 2019-11-12 19:07:05 +01:00
Garrett 3a19ba7e62 added docstrings to ad9910.py 2019-11-12 19:07:05 +01:00
Garrett 4ad3651022 fixed typo in ad9910.py 2019-11-12 19:07:05 +01:00
Garrett 6d34eb3bb0 updated docstrings for set_cfr1() in ad9910.py 2019-11-12 19:07:05 +01:00
Garrett 61ca46ec3f updated adoo10.py for RAM mode frequency control 2019-11-12 19:07:05 +01:00
Sebastien Bourdeauducq 5279bc275a urukul: rework EEPROM synchronization. Closes #1372 2019-11-05 18:56:10 +08:00
Robert Jördens 1f15e55021 comm_analyzer: don't assume every message has data 
close #1377
 2019-10-28 15:35:44 +01:00
Sebastien Bourdeauducq a8f85860c4 coreanalyzer: AD9914 fixes (#1376) 2019-10-17 07:29:33 +08:00
Tim Ballance ada3b39f4e Fix ad9910 ram mode asf scale error in polar mode 2019-10-04 20:14:41 +02:00
Tim Ballance 448080e71d Fix ad9910 ram mode asf scale error 
RAM mode amplitude to ASF conversion should be << 18 rather than << 16
 2019-10-04 20:14:41 +02:00
Sebastien Bourdeauducq 98cd9a539c compiler: support Cortex A9 target 2019-08-26 10:46:22 +08:00
David Nadlinger 99e490f9ff coredevice/suservo: Slightly reword get_adc[_mu]() docstring for clarity 
This hopefully suggests a bit better that the value is the last one
fetched by the servo (i.e. needs the servo active to update), rather
than somehow requesting a new sample to be taken.
 2019-07-30 12:22:08 +01:00
Sebastien Bourdeauducq b8870997d0 doc: clarify TTL direction control with buffered cards 2019-07-24 10:04:45 +08:00
David Nadlinger 280915d54f coredevice/suservo: Adjust T_CYCLE to match gateware 
See GitHub #1338.
 2019-07-17 00:20:22 +01:00
Robert Jördens f7e10759dc suservo: note requirement to stop servo when accessing state 
As already mentioned in the gateware.

One alternative would be to detect address collisions and
stall the read for one cycle.

Note that there will in general not be a consistent view of the servo
state unless the servo is stopped.

close #1337
 2019-07-08 18:37:42 +02:00
David Nadlinger 8bf9640185 coredevice/suservo: Fix output IIR state width in docstring 2019-06-21 11:27:39 +02:00
David Nadlinger 34f48f57cc coredevice/suservo: Fix {get,set}_y_mu() scaling 
Previously, Channel.set_y(1) would set the output to -1 instead.
 2019-06-21 11:27:39 +02:00
Sebastien Bourdeauducq 74e4b01201 urukul: document consequences of incorrect CPLD clock settings 2019-06-11 11:12:12 +08:00
Brad Bondurant adf3df2bb5 suservo coredevice driver: mask ftw to avoid erroneous sign extension 2019-06-03 21:40:04 +02:00
David Nadlinger fc95183e04 coredevice: Fix host-side serialization of (nested) lists 
Test case to follow.
 2019-03-31 17:10:27 +01:00
Sebastien Bourdeauducq d07c6fcfea ad9910: handle unprogrammed EEPROM and numpy corner cases 2019-03-22 14:28:47 +08:00
Sebastien Bourdeauducq 04e0c23e78 ad9910: support reading synchronization values from EEPROM 2019-03-13 15:34:47 +08:00
Sebastien Bourdeauducq 964a349a19 add Kasli I2C driver 2019-03-13 15:33:50 +08:00
Sebastien Bourdeauducq 227c729f56 fix permissions 2019-03-11 20:43:28 +08:00
Robert Jördens aee8965897 ad9910: add ram conversion tooling and unittests 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2019-02-21 15:59:52 +00:00
Robert Jördens b57cad77ad ad9910: make ram read work for short segments 
also cleanup and style

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2019-02-21 14:47:58 +00:00
hartytp 0ebff04ad7 SUServo: apply bit masks to servo memory writes to prevent overflows 
Signed-off-by: TPH <thomas.harty@physics.ox.ac.uk>
 2019-02-07 17:04:11 +01:00
hartytp f6142816b8
Revert "SUServo: remove references to non-existent a0 parameter" (#1270) 
This reverts commit f3aab2b891.

Signed-off-by: TPH <thomas.harty@physics.ox.ac.uk>
 2019-02-07 15:57:43 +00:00
hartytp fe63c9b366
SUServo: remove references to non-existent a0 parameter (#1268) 
Signed-off-by: Thomas Harty <thomas.harty@physics.ox.ac.uk>
 2019-02-07 15:29:32 +00:00
hartytp df6c1fca2c
SUServo: flake8 [NFC] (#1267) 
Signed-off-by: Thomas Harty <thomas.harty@physics.ox.ac.uk>
 2019-02-07 15:13:44 +00:00
Robert Jördens 8c5a502591 ad53xx: ignore F3 (reserved) 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2019-01-24 15:50:46 +01:00
Sebastien Bourdeauducq 330c5610e9 ad9912: fix imports 2019-01-23 17:59:08 +08:00
Robert Jördens b692981c8e ad9910: add note about red front panel led 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2019-01-22 12:49:42 +01:00
Robert Jördens 91e375ce6a ad9910: don't reset the input divide-by-two 
suspected of causing weird PLL lock timout errors
https://freenode.irclog.whitequark.org/m-labs/2019-01-22#1548148750-1548143221;

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2019-01-22 09:37:20 +00:00
Robert Jördens 81ff3d4b29 ad9912: add some slack after init 2019-01-21 17:10:58 +00:00
Sebastien Bourdeauducq 84f7d006e8 ad9910: add precision about tune_io_update_delay/tune_sync_delay order 2019-01-21 19:40:55 +08:00
Sebastien Bourdeauducq 30051133b7 urukul: fix typos 2019-01-21 19:40:55 +08:00
Robert Jördens 40187d1957 ad9910: support configurable refclk divider and pll bypass 
for #1248

* also always keep refclk input divider (by two) reset
 2019-01-18 12:23:53 +00:00
Robert Jördens 385916a9a4 ad9912: support configurable clk_div 2019-01-18 12:16:08 +00:00
Robert Jördens 2bea5e3d58 urukul: support configurable refclk divider 
for #1248
 2019-01-18 12:09:32 +00:00
David Nadlinger a565f77538 Add gateware input event counter 2019-01-15 10:55:07 +00:00
David Nadlinger 6c52359e59 coredevice: Add _mu suffix to AD991x ref_time arguments 
GitHub: Fixes #1243.
 2019-01-12 17:34:35 +00:00
whitequark 49682d0159 Improve Python 3.7 compatibility. 
async is now a full (non-contextual) keyword.

There are two more instances:
   - artiq/frontend/artiq_client.py
   - artiq/devices/thorlabs_tcube/driver.py

It is not immediately clear how to fix those, so they are left for
later work.
 2019-01-12 13:17:59 +00:00
David Nadlinger 48fc175a6b coredevice.ttl: More imperative mood in docstrings [nfc] 
This follows Python conventions (PEP257) and unifies the style with
other comments.
 2019-01-12 12:01:55 +00:00
David Nadlinger 3e84ec2bf1 coredevice.ad9910: Fix phase tracking ref_time passing 
This is difficult to test without hardware mocks or some
form of phase readback, but the symptom was that e.g.
`self.dds.set(…, ref_time=now_mu() - 1)` would fail
periodically, that is, whenever bit 32 of the timestamp
would be set (which would be turned into the sign bit).

This is a fairly sinister issue, and is probably a compiler
bug of some sort (either accepts-invalid or wrong type inference).
 2019-01-12 00:47:38 +00:00
Robert Jördens 101671fbbf core_analyzer: support uniform VCD time intervals 
close #1236

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2019-01-10 19:35:09 +01:00
Robert Jördens 19748fe495 ad9910: fix RTIO fine timestamp nudging 
Previously the TSC was truncated to an even coarse RTIO periods before doing
the setting SPI xfer. Afterwards the the IO update pulse would introduce
at least one but less than two RTIO cycles. Ultimately the RTIO TSC was
truncated again to even. If the SPI xfer takes an odd number of RTIO
periods, then a subsequent xfer would collide.

close #1229

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2019-01-09 17:22:57 +00:00
Robert Jördens b25ab1fc88 ad9910: add more slack in tune_sync_delay 
close #1235

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2019-01-09 16:07:31 +00:00
Drew 40370c4d45 Docs: fix build warnings (#1234) 
* ad9910: finish CONT_RECIRCULATE -> CONT_RAMPUP

Found while building docs. Forgot to refactor strings.

Signed-off-by: Drew Risinger <drewrisinger@users.noreply.github.com>

* spi2: reformat update_xfer_duration_mu docstring

update_xfer_duration_mu docstring threw warning while building docs,
didn't use consistent indent in warning.

Signed-off-by: Drew Risinger <drewrisinger@users.noreply.github.com>
 2019-01-09 11:39:23 +08:00
David Nadlinger 4fb434674d coredevice: Fix ad9910 __all__ exports 2019-01-08 18:55:26 +00:00
David Nadlinger cadde970e1 urukul: Expand CPLD sync_sel explanation [nfc] 2019-01-08 02:37:58 +00:00
David Nadlinger 7bcdeb825b ad9910: Add inverse FTW/ASF conversions 2019-01-08 02:18:14 +00:00
David Nadlinger 4d793d7149 ad9910: Truncate phase word to 16 bits 
This avoids overflowing into the asf portion of the register.
 2019-01-08 02:18:14 +00:00
Robert Jördens a7d4d3bda9 ad9910: CONT_RECIRCULATE -> CONT_RAMPUP 2018-12-17 13:25:00 +00:00
Sebastien Bourdeauducq 35bdf26f01 Merge branch 'ad9910-ram' 2018-12-17 21:16:44 +08:00
David Nadlinger e608d6ffd3 coredevice, firmware: Add rtio_input_timestamped_data 
Integration tests to follow as part of an RTIO counter phy that
makes use of this.
 2018-12-15 00:35:04 +00:00
Robert Jördens 79eadb9465 ad9910: add RAM mode methods 
* also refactor the CFR1 access into a method

c.f. #1154

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-12-11 14:54:16 +00:00
Robert Jördens efd400b02c ad9910: style [nfc] 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-12-11 11:36:25 +01:00
Robert Jördens d90eb3ae88 ad9910: add read64() 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-12-07 21:27:00 +00:00
Robert Jördens baf88050fd urukul: expand attenuator HITL unittests 
* read back with cleared backing state
* individual channel settings
* check backing state

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-12-07 21:06:12 +00:00
Sebastien Bourdeauducq dce4f036db grabber: work around windows numpy int peculiarity (same as a81c12de9) 2018-11-30 18:41:14 +08:00
Sebastien Bourdeauducq 450a035f9e suservo: move overflowing RTIO address bits into data 2018-11-26 06:54:20 +08:00
Sebastien Bourdeauducq b32e89444c Merge branch 'master' into new 2018-11-26 01:02:19 +08:00
Robert Jördens a81c12de94 urukul: work around windows numpy int peculiarity 
"OverflowError: Python int too large to convert to C long" otherwise

opticlock#74

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-25 16:56:45 +01:00
Sebastien Bourdeauducq 8f9858be4c ad9914: remove automatic continuous phase compensation (like Urukul) 2018-11-19 22:00:20 +08:00
Sebastien Bourdeauducq 53e79f553f Merge branch 'master' into new 2018-11-19 11:54:50 +08:00
Sebastien Bourdeauducq a3e0b1c5b4 ad9914,spi2: add warnings about driver state and DMA. Closes #1113 2018-11-17 22:10:20 +08:00
Sebastien Bourdeauducq 69e699c7bd ttl: compensate for SED latency in input gating 
Closes #1137
 2018-11-17 22:10:20 +08:00
Robert Jördens 3ad68f65c5 urukul: make get_att_mu() not alter state 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-16 14:56:26 +00:00
Robert Jördens d1eee7c0ea ad9910: ensure sync is driven when required 
close #1194

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-16 13:21:01 +00:00
Sebastien Bourdeauducq 1b841805f6 Merge branch 'master' into new 2018-11-16 15:20:32 +08:00
Robert Jördens c3178c2cab ad9910: profile support 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-14 08:30:28 +01:00
Robert Jördens d0cadfeb4b ad9910: more idiomatic register names 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-14 07:55:01 +01:00
Robert Jördens a52d1be140 urukul: expose PROFILE setting 
* add documentation
* add unittest

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-14 07:43:56 +01:00
Robert Jördens a4997c56cf ad9910: simplify edge detection logic 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-09 18:54:34 +00:00
Robert Jördens 14b6b63916 ad9910: rewire io_delay tuning 
This now reliably locates the SYNC_CLK-IO_UPDATE edge by doing two
scans at different delays between start and stop IO_UPDATE.
It also works well when one delay is very close to the edge.
And it correctly identifies which (start or stop) pulse hit or crossed
the SYNC_CLK edge.

for #1143

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-09 18:38:27 +00:00
Robert Jördens 38c6878d49 urukul: mention min/max attenuation 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-09 13:32:05 +01:00
Robert Jördens e565ca6b82 urukul: slow down att write to datasheet limit 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-09 13:23:06 +01:00
Robert Jördens 998be50f07 urukul: handle MSB in att_reg 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-09 13:21:14 +01:00
Sebastien Bourdeauducq c990b5e4f1 Merge remote-tracking branch 'origin/master' into new 2018-11-08 20:21:56 +08:00
Sebastien Bourdeauducq 0bee43aa58 sawg: use new rtio_output() API 2018-11-08 20:16:30 +08:00
Sebastien Bourdeauducq bec25cbaa0 suservo: use new rtio_output() API 2018-11-08 20:13:14 +08:00
Sebastien Bourdeauducq e8d58b35b4 spi2: use new rtio_output() API 2018-11-08 20:12:30 +08:00
Sebastien Bourdeauducq d18546550e grabber: use new rtio_output() API 2018-11-08 19:15:50 +08:00
Sebastien Bourdeauducq 2549e623c1 ad9914: use new rtio_output() API 2018-11-08 19:15:44 +08:00
Sebastien Bourdeauducq 8caea0e6d3 gateware,runtime: optimize RTIO kernel interface further 
* now pinning (TODO: atomicity)
* for inputs, merge request and timeout registers
 2018-11-08 18:29:24 +08:00
Sebastien Bourdeauducq fae95e73ad ttl: use optimized rtio_output API 2018-11-07 23:41:43 +08:00
Sebastien Bourdeauducq 3d0c3cc1cf gateware,runtime: optimize RTIO output interface 
* reduce address to 8 bits
* merge core, channel and address into 32-bit pre-computable "target"
* merge we register into data register
 2018-11-07 23:39:58 +08:00
Robert Jördens e6efe830c4 ad9910: rewire sync delay tuning 
* search from wide window end
* decouple margins and minimum window size
* add note about kasli jitter

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-07 14:52:03 +00:00
Sebastien Bourdeauducq ad0254c17b Merge branch 'switching125' into new 2018-11-07 22:03:18 +08:00
Robert Jördens 6c00ab57c0 test_ad9910: relax SYNC window 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-06 19:31:38 +01:00
Robert Jördens 172633c7da test_ad9910: default to a useful seed 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-06 17:35:57 +01:00
Robert Jördens 0b2661a34d ad9910: robustify SYNC window finding 
don't integrate too long, find the window tip fast and early
a couple 100 SYNC pulses are sufficient

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-06 12:41:21 +00:00
Robert Jördens 31f68ddf6c Merge branch 'urukul-sync' 
* urukul-sync: (29 commits)
  urukul: flake8 [nfc]
  ad9910: flake8 [nfc]
  urukul/ad9910 test: remove unused import
  test_urukul: relax speed
  urukul,ad9910: print speed metrics
  kasli: add PTB2 (external clock and SYNC)
  kasli: add sync to LUH, HUB, Opticlock
  kasli_tester: urukul0 mmcx clock defunct
  test_ad9910: relax ifc mode read
  tests: add Urukul-AD9910 HITL unittests including SYNC
  ad9910: add init bit explanation
  test: add Urukul CPLD HITL tests
  ad9910: fiducial timestamp for tracking phase mode
  ad9910: add phase modes
  ad9910: fix pll timeout loop
  tester: add urukul sync
  ptb: back out urukul-sync
  ad9910: add IO_UPDATE alignment and tuning
  urukul: set up sync_in generator
  ad9910: add io_update alignment measurement
  ...

close #1143
 2018-11-05 19:54:30 +01:00
Robert Jördens 6fb18270a2 urukul: flake8 [nfc] 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:45:24 +01:00
Robert Jördens 832690af9a ad9910: flake8 [nfc] 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:44:51 +01:00
Robert Jördens 9fb850ae75 ad9910: add init bit explanation 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:37:02 +01:00
Robert Jördens bc04da15c5 test: add Urukul CPLD HITL tests 
for #1143

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:37:00 +01:00
Robert Jördens 141cc7d99f ad9910: fiducial timestamp for tracking phase mode 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:36:58 +01:00
Robert Jördens 2f6d3f79ff ad9910: add phase modes 
* simplified and cross-referenced the explanation of the different
  phase modes.
* semantically and functionally merged absolute and tracking/coherent
  phase modes.
* simplified numerics to calculate phase correction
* added warning about possible inconsistency with DMA and default
  phase mode
* restricted __all__ imports
* moved continuous/relative phase offset tracking from an instance
  variable to a "handle" returned by set()/set_mu() in order to avoid
  state inconsistency with DMA (#1113 #1115)

for #1143

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:36:55 +01:00
Robert Jördens d3ad2b7633 ad9910: fix pll timeout loop 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:36:53 +01:00
Robert Jördens 06139c0f4d ad9910: add IO_UPDATE alignment and tuning 
for #1143

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:36:48 +01:00
Robert Jördens 1066430fa8 urukul: set up sync_in generator 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:36:46 +01:00
Robert Jördens 4bbd833cfe ad9910: add io_update alignment measurement 
for #1143

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:36:44 +01:00
Robert Jördens 7b92282012 ad9910: add docs for sync tuning, refactor 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:36:42 +01:00
Robert Jördens 8a47a6b2fb ad9910: disable sync_clk output 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:36:40 +01:00
Robert Jördens 65e2ebf960 ad9910: add sync delay control, auto tuning 
* expose multi device sync functionality
* sync delay configuration interface
* auto-tuning of sync delay from device_db seed

for #1143

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:36:37 +01:00
Robert Jördens 8dbf5f87fd ad9910: simplify io_update pulsing on init, set_mu 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:36:35 +01:00
Robert Jördens 0b3b07a7da ad9910: add power down method 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:36:34 +01:00
Robert Jördens 0433e8f4fe urukul: add sync_in generator 
for #1143

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:36:30 +01:00
Robert Jördens f62c1ff0bb TTLClockGen: expose acc_width 
Signed-off-by: Robert Jördens <rj@quartiq.de>
 2018-11-05 19:36:27 +01:00
David Nadlinger f79b9d9e1e ttl: Expand input gate/count API docstrings 2018-11-03 20:33:19 +08:00
David Nadlinger 5d2e3f975f coredevice: Add get_rtio_counter_mu() docstring [nfc] 2018-11-03 20:33:19 +08:00
David Nadlinger d6fcc0529f coredevice: Imperative mood in docstrings [nfc] 
This follows Python conventions (PEP257) and unifies the style with
other comments.
 2018-11-03 20:33:19 +08:00
David Nadlinger cbdef0225c ttl: Add target RTIO time argument to timestamp/count functions 
Software-based tracking of timestamps is problematic (e.g. when
using DMA, see GitHub #1113).
 2018-11-03 20:33:19 +08:00
David Nadlinger 2a0e1dabfb ttl: Remove unused attribute [nfc] 2018-11-03 20:33:19 +08:00
David Nadlinger 17a5fb2dce ttl: Remove error-prone sync() calls 
These methods are problematic, as with DMA in the picture, the
timestamp member variables did not necessarily reflect the last
submitted event timestamp (see GitHub #1113).

sync() is only very rarely used in typical experimental code, so
the methods are removed without a transition period.
Core.wait_until() can be used to busy-wait for a specified RTIO
timestamp value on the core device CPU instead.
 2018-11-03 20:33:19 +08:00
David Nadlinger 11e8c9d5f7 coredevice: Add Core.wait_until_mu() 
(This supersedes TTLOut.sync(), see see GitHub #1113.)
 2018-11-03 20:33:19 +08:00
David Nadlinger cbfbe24d7a ttl: Remove broken TTLClockGen.sync 
The code currently doesn't compile because of a typo in the timestamp
field name. However, tracking event timestamps in software is
problematic anyway (e.g. with DMA, see GitHub #1113), so just remove
`sync()` altogether.
 2018-11-03 20:33:19 +08:00
Robert Jördens 89a961fb00 urukul, ad9912, ad9910: expose CFG RF switch better 
* conincident setting of multiple switches
* per channel setting
 2018-10-24 13:04:46 +02:00
Robert Jördens 661dd00c4c ad9912: phase offset is 14 bit LSB aligned 
c.f. sinara-hw/Urukul#15
 2018-10-11 15:16:08 +02:00
hartytp 08074d5275 Urukul: add support for hardware v1.3 clocking options 2018-10-10 09:26:35 +02:00
hartytp 1a1b454ed9 Urukul: flake8 (NFC) 2018-10-08 10:09:49 +01:00
hartytp 9a509e5070 Zotino: increase delay after register read in init method to avoid underflows 2018-10-06 21:45:17 +08:00
Sebastien Bourdeauducq 969a305c5a Merge branch 'master' into switching125 2018-10-04 10:08:42 +08:00
Sebastien Bourdeauducq c71e442929 documentation improvements 
Based on PR #1101 by @drewrisinger
 2018-09-26 12:12:37 +08:00
Sebastien Bourdeauducq c8cd830118 drtio: implement get_rtio_destination_status for kernels 2018-09-15 19:11:22 +08:00
Sebastien Bourdeauducq d38755feff drtio: implement destination state checks on operations 2018-09-15 15:55:45 +08:00
Sebastien Bourdeauducq 95432a4ac1 drtio: remove old debugging features 2018-09-12 13:01:27 +08:00
whitequark a74958f01f ksupport: raise RuntimeError on reraise with no inflight exception. 
Fixes #1123.
 2018-08-07 05:53:13 +00:00
Chris Ballance 6fc8439399 tweak moninj to allow old dashboard with new firmware 2018-08-02 19:34:14 +08:00