mirror of https://github.com/m-labs/artiq.git
phaser: init [wip]
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07418258ae
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@ -129,18 +129,20 @@ class Phaser:
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self.channel = [PhaserChannel(self, ch) for ch in range(2)]
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self.channel = [PhaserChannel(self, ch) for ch in range(2)]
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@kernel
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@kernel
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def init(self):
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def init(self, clk_sel=0):
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"""Initialize the board.
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"""Initialize the board.
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Verifies board and chip presence, resets components, performs communication
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Verifies board and chip presence, resets components, performs communication
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and configuration tests and establishes initial conditions.
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and configuration tests and establishes initial conditions.
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:param clk_sel: Select the external SMA clock input (1 or 0)
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"""
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"""
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board_id = self.read8(PHASER_ADDR_BOARD_ID)
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board_id = self.read8(PHASER_ADDR_BOARD_ID)
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if board_id != PHASER_BOARD_ID:
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if board_id != PHASER_BOARD_ID:
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raise ValueError("invalid board id")
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raise ValueError("invalid board id")
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delay(20*us) # slack
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delay(20*us) # slack
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# allow a few errors during startup and alignment
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# allow a few errors during startup and alignment
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if self.get_crc_err() > 20:
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if self.get_crc_err() > 20:
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raise ValueError("large number of CRC errors")
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raise ValueError("large number of CRC errors")
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delay(.1*ms) # slack
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delay(.1*ms) # slack
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@ -148,7 +150,7 @@ class Phaser:
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self.set_cfg(dac_resetb=0, att0_rstn=0, att1_rstn=0)
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self.set_cfg(dac_resetb=0, att0_rstn=0, att1_rstn=0)
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self.set_leds(0x00)
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self.set_leds(0x00)
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self.set_fan_mu(0)
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self.set_fan_mu(0)
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self.set_cfg() # bring everything out of reset
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self.set_cfg(clk_sel=clk_sel) # bring everything out of reset
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delay(.1*ms) # slack
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delay(.1*ms) # slack
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# 4 wire SPI, sif4_enable
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# 4 wire SPI, sif4_enable
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@ -165,6 +167,43 @@ class Phaser:
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raise ValueError("DAC temperature out of bounds")
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raise ValueError("DAC temperature out of bounds")
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delay(.1*ms)
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delay(.1*ms)
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delay(.5*ms) # slack
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self.dac_write(0x00, 0x019c) # I=2, fifo, clkdiv_sync, qmc off
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self.dac_write(0x01, 0x040e) # fifo alarms, parity
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self.dac_write(0x02, 0x70a2) # clk alarms, sif4, nco off, mix, mix_gain, 2s
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self.dac_write(0x03, 0x6000) # coarse dac 20.6 mA
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self.dac_write(0x07, 0x40c1) # alarm mask
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self.dac_write(0x09, 0x8000) # fifo_offset
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self.dac_write(0x0d, 0x0000) # fmix, no cmix
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self.dac_write(0x14, 0x5431) # fine nco ab
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self.dac_write(0x15, 0x0323) # coarse nco ab
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self.dac_write(0x16, 0x5431) # fine nco cd
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self.dac_write(0x17, 0x0323) # coarse nco cd
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self.dac_write(0x18, 0x2c60) # P=4, pll run, single cp, pll_ndivsync
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self.dac_write(0x19, 0x8404) # M=8 N=1
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self.dac_write(0x1a, 0xfc00) # pll_vco=63
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delay(.2*ms) # slack
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self.dac_write(0x1b, 0x0800) # int ref, fuse
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self.dac_write(0x1e, 0x9999) # qmc sync from sif and reg
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self.dac_write(0x1f, 0x9982) # mix sync, nco sync, istr is istr, sif_sync
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self.dac_write(0x20, 0x2400) # fifo sync ISTR-OSTR
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self.dac_write(0x22, 0x1be4) # reverse dacs for spectral inversion and layout
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self.dac_write(0x24, 0x0000) # clk and data delays
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delay(1*ms) # lock pll
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lvolt = self.dac_read(0x18) & 7
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delay(.1*ms)
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if lvolt < 2 or lvolt > 5:
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raise ValueError("DAC PLL tuning voltage out of bounds")
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self.dac_write(0x20, 0x0000) # stop fifo sync
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self.dac_write(0x05, 0x0000) # clear alarms
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delay(1*ms) # run it
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alarm = self.get_sta() & 1
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delay(.1*ms)
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if alarm:
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alarm = self.dac_read(0x05)
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raise ValueError("DAC alarm")
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patterns = [
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patterns = [
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[0xffff, 0xffff, 0x0000, 0x0000], # test channel
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[0xffff, 0xffff, 0x0000, 0x0000], # test channel
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[0xaa55, 0x55aa, 0x55aa, 0xaa5a], # test iq
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[0xaa55, 0x55aa, 0x55aa, 0xaa5a], # test iq
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@ -173,11 +212,18 @@ class Phaser:
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[0x1a1a, 0x1616, 0xaaaa, 0xc6c6], # ds pattern b
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[0x1a1a, 0x1616, 0xaaaa, 0xc6c6], # ds pattern b
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]
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]
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delay(.5*ms)
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delay(.5*ms)
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for i in range(len(patterns)):
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# A data delay of 3*50 ps heuristically matches FPGA+board+DAC skews.
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errors = self.dac_iotest(patterns[i])
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# There is plenty of margin and no need to tune at runtime.
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if errors:
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# Parity provides another level of safety.
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raise ValueError("iotest error")
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for dly in [-3]: # range(-7, 8)
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delay(.5*ms)
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if dly < 0:
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dly = -dly << 3 # data delay, else clock delay
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self.dac_write(0x24, dly << 10)
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for i in range(len(patterns)):
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errors = self.dac_iotest(patterns[i])
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if errors:
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raise ValueError("iotest error")
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delay(.5*ms)
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hw_rev = self.read8(PHASER_ADDR_HW_REV)
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hw_rev = self.read8(PHASER_ADDR_HW_REV)
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has_upconverter = hw_rev & PHASER_HW_REV_VARIANT
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has_upconverter = hw_rev & PHASER_HW_REV_VARIANT
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@ -424,26 +470,18 @@ class Phaser:
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# dac test data is i msb, q lsb
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# dac test data is i msb, q lsb
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self.channel[ch].set_dac_test(pattern[2*ch] | (pattern[2*ch + 1] << 16))
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self.channel[ch].set_dac_test(pattern[2*ch] | (pattern[2*ch + 1] << 16))
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self.dac_write(0x01, 0x8000) # iotest_ena
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self.dac_write(0x01, 0x8000) # iotest_ena
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errors = 0
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self.dac_write(0x04, 0x0000) # clear iotest_result
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# A data delay of 3*50 ps heuristically matches FPGA+board+DAC skews.
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delay(.2*ms) # let it rip
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# There is plenty of margin and no need to tune at runtime.
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# no need to go through the alarm register,
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# Parity provides another level of safety.
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# just read the error mask
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for dly in [-3]: # range(-7, 8)
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# self.dac_write(0x05, 0x0000) # clear alarms
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if dly < 0:
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# alarm = self.dac_read(0x05)
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dly = -dly << 3 # data delay, else clock delay
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# delay(.1*ms) # slack
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self.dac_write(0x24, dly << 10)
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# if alarm & 0x0080: # alarm_from_iotest
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self.dac_write(0x04, 0x0000) # clear iotest_result
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errors = self.dac_read(0x04)
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delay(.2*ms) # let it rip
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delay(.1*ms) # slack
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# no need to go through the alarm register,
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self.dac_write(0x01, 0x0000) # clear config
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# just read the error mask
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self.dac_write(0x04, 0x0000) # clear iotest_result
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# self.dac_write(0x05, 0x0000) # clear alarms
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# alarm = self.dac_read(0x05)
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# delay(.1*ms) # slack
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# if alarm & 0x0080: # alarm_from_iotest
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errors |= self.dac_read(0x04)
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delay(.1*ms) # slack
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self.dac_write(0x24, 0) # reset delays
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# self.dac_write(0x01, 0x0000) # clear config
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return errors
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return errors
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