From fe6a5c42dfac0d847540d27b6d9fa619263f1fe2 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 27 Jul 2015 10:57:15 +0800 Subject: [PATCH] rtio: remove unused clk_freq argument --- artiq/gateware/rtio/core.py | 3 +-- soc/targets/artiq_kc705.py | 3 +-- soc/targets/artiq_pipistrello.py | 3 +-- 3 files changed, 3 insertions(+), 6 deletions(-) diff --git a/artiq/gateware/rtio/core.py b/artiq/gateware/rtio/core.py index 38446604e..bb5b51efe 100644 --- a/artiq/gateware/rtio/core.py +++ b/artiq/gateware/rtio/core.py @@ -300,8 +300,7 @@ class _KernelCSRs(AutoCSR): class RTIO(Module): - def __init__(self, channels, clk_freq, full_ts_width=63, - guard_io_cycles=20): + def __init__(self, channels, full_ts_width=63, guard_io_cycles=20): data_width = max(rtlink.get_data_width(c.interface) for c in channels) address_width = max(rtlink.get_address_width(c.interface) diff --git a/soc/targets/artiq_kc705.py b/soc/targets/artiq_kc705.py index cfc9774f9..666cb8f05 100644 --- a/soc/targets/artiq_kc705.py +++ b/soc/targets/artiq_kc705.py @@ -58,8 +58,7 @@ class _NIST_QCx(MiniSoC, AMPSoC): def add_rtio(self, rtio_channels): self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.pll_sys) - self.submodules.rtio = rtio.RTIO(rtio_channels, - clk_freq=125000000) + self.submodules.rtio = rtio.RTIO(rtio_channels) self.add_constant("RTIO_FINE_TS_WIDTH", self.rtio.fine_ts_width) self.add_constant("DDS_RTIO_CLK_RATIO", 8 >> self.rtio.fine_ts_width) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) diff --git a/soc/targets/artiq_pipistrello.py b/soc/targets/artiq_pipistrello.py index fd09ed373..e393edc36 100644 --- a/soc/targets/artiq_pipistrello.py +++ b/soc/targets/artiq_pipistrello.py @@ -128,8 +128,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd # RTIO core self.submodules.rtio_crg = _RTIOCRG(platform, self.clk_freq) - self.submodules.rtio = rtio.RTIO(rtio_channels, - clk_freq=125000000) + self.submodules.rtio = rtio.RTIO(rtio_channels) self.add_constant("RTIO_FINE_TS_WIDTH", self.rtio.fine_ts_width) self.add_constant("DDS_RTIO_CLK_RATIO", 8 >> self.rtio.fine_ts_width) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)