diff --git a/artiq/gateware/drtio/wrpll/__init__.py b/artiq/gateware/drtio/wrpll/__init__.py
index e69de29bb..d004bc955 100644
--- a/artiq/gateware/drtio/wrpll/__init__.py
+++ b/artiq/gateware/drtio/wrpll/__init__.py
@@ -0,0 +1 @@
+from artiq.gateware.drtio.wrpll.core import WRPLL
diff --git a/artiq/gateware/drtio/wrpll/core.py b/artiq/gateware/drtio/wrpll/core.py
new file mode 100644
index 000000000..77c11fb3b
--- /dev/null
+++ b/artiq/gateware/drtio/wrpll/core.py
@@ -0,0 +1,10 @@
+from migen import *
+from misoc.interconnect.csr import *
+
+from artiq.gateware.drtio.wrpll.si549 import Si549
+
+
+class WRPLL(Module, AutoCSR):
+	def __init__(self, main_dcxo_i2c, helper_dxco_i2c):
+		self.submodules.main_dcxo = Si549(main_dcxo_i2c)
+		self.submodules.helper_dcxo = Si549(helper_dxco_i2c)
diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py
index 95d2347b0..76cc455af 100755
--- a/artiq/gateware/targets/sayma_amc.py
+++ b/artiq/gateware/targets/sayma_amc.py
@@ -19,6 +19,7 @@ from artiq.gateware import jesd204_tools
 from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_ultrascale, sawg
 from artiq.gateware.drtio.transceiver import gth_ultrascale
 from artiq.gateware.drtio.siphaser import SiPhaser7Series
+from artiq.gateware.drtio.wrpll import WRPLL
 from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
 from artiq.gateware.drtio import *
 from artiq.build_soc import *
@@ -51,7 +52,7 @@ class SatelliteBase(MiniSoC):
     }
     mem_map.update(MiniSoC.mem_map)
 
-    def __init__(self, rtio_clk_freq=125e6, identifier_suffix="", **kwargs):
+    def __init__(self, rtio_clk_freq=125e6, identifier_suffix="", *, with_wrpll, **kwargs):
         MiniSoC.__init__(self,
                  cpu_type="or1k",
                  sdram_controller_type="minicon",
@@ -141,6 +142,17 @@ class SatelliteBase(MiniSoC):
         self.config["I2C_BUS_COUNT"] = 1
         self.config["HAS_SI5324"] = None
 
+        if with_wrpll:
+            # TODO: check OE polarity (depends on what was installed on the boards)
+            self.comb += [
+                platform.request("ddmtd_main_dcxo_oe").eq(1),
+                platform.request("ddmtd_helper_dcxo_oe").eq(1)
+            ]
+            self.submodules.wrpll = WRPLL(
+                main_dcxo_i2c=platform.request("ddmtd_main_dcxo_i2c"),
+                helper_dxco_i2c=platform.request("ddmtd_helper_dcxo_i2c"))
+            self.csr_devices.append("wrpll")
+
         rtio_clk_period = 1e9/rtio_clk_freq
         gth = self.drtio_transceiver.gths[0]
         platform.add_period_constraint(gth.txoutclk, rtio_clk_period/2)
@@ -492,13 +504,15 @@ def main():
         default=False, action="store_true",
         help="Remove SAWG RTIO channels feeding the JESD links (speeds up "
         "compilation time). Replaces them with fixed pattern generators.")
+    parser.add_argument("--with-wrpll", default=False, action="store_true")
     args = parser.parse_args()
 
     variant = args.variant.lower()
     if variant == "satellite":
-        soc = Satellite(with_sawg=not args.without_sawg, **soc_sayma_amc_argdict(args))
+        soc = Satellite(with_sawg=not args.without_sawg, with_wrpll=args.with_wrpll,
+                        **soc_sayma_amc_argdict(args))
     elif variant == "simplesatellite":
-        soc = SimpleSatellite(**soc_sayma_amc_argdict(args))
+        soc = SimpleSatellite(with_wrpll=args.with_wrpll, **soc_sayma_amc_argdict(args))
     elif variant == "master":
         soc = Master(**soc_sayma_amc_argdict(args))
     else: