From fdb2867757754ea36a4c220bafcc09d53acb139e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Mon, 21 Sep 2020 17:06:26 +0200 Subject: [PATCH] phaser: fewer iotest patterns --- artiq/coredevice/phaser.py | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/artiq/coredevice/phaser.py b/artiq/coredevice/phaser.py index f28fbe69e..1c45ab783 100644 --- a/artiq/coredevice/phaser.py +++ b/artiq/coredevice/phaser.py @@ -173,11 +173,9 @@ class Phaser: delay(.5*ms) patterns = [ - [0xffff, 0xffff, 0x0000, 0x0000], # test channel - [0xaa55, 0x55aa, 0x55aa, 0xaa5a], # test iq - [0xaa55, 0xaa55, 0x55aa, 0x55aa], # test byte - [0x7a7a, 0xb6b6, 0xeaea, 0x4545], # ds pattern a - [0x1a1a, 0x1616, 0xaaaa, 0xc6c6], # ds pattern b + [0xf05a, 0x05af, 0x5af0, 0xaf05], # test channel/iq/byte/nibble + [0x7a7a, 0xb6b6, 0xeaea, 0x4545], # datasheet pattern a + [0x1a1a, 0x1616, 0xaaaa, 0xc6c6], # datasheet pattern b ] # A data delay of 2*50 ps heuristically and reproducibly matches # FPGA+board+DAC skews. There is plenty of margin (>= 250 ps