mirror of https://github.com/m-labs/artiq.git
artiq_ddb_template: fix clk_div config
remove clk_div default in jsonschema set CLK IN divided by 1 as default when bypassing PLL
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@ -308,8 +308,7 @@
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"clk_div": {
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"type": "integer",
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"minimum": 0,
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"maximum": 3,
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"default": 0
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"maximum": 3
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},
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"pll_n": {
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"type": "integer"
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@ -211,6 +211,11 @@ class PeripheralManager:
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urukul_name = self.get_name("urukul")
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synchronization = peripheral["synchronization"]
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channel = count(0)
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pll_en = peripheral["pll_en"]
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clk_div = peripheral.get("clk_div")
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if clk_div is None:
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clk_div = 0 if pll_en else 1
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self.gen("""
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device_db["eeprom_{name}"] = {{
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"type": "local",
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@ -277,7 +282,7 @@ class PeripheralManager:
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sync_device="\"ttl_{name}_sync\"".format(name=urukul_name) if synchronization else "None",
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refclk=peripheral.get("refclk", self.primary_description["rtio_frequency"]),
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clk_sel=peripheral["clk_sel"],
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clk_div=peripheral["clk_div"])
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clk_div=clk_div)
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dds = peripheral["dds"]
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pll_vco = peripheral.get("pll_vco")
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for i in range(4):
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@ -299,7 +304,7 @@ class PeripheralManager:
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uchn=i,
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sw=",\n \"sw_device\": \"ttl_{name}_sw{uchn}\"".format(name=urukul_name, uchn=i) if len(peripheral["ports"]) > 1 else "",
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pll_vco=",\n \"pll_vco\": {}".format(pll_vco) if pll_vco is not None else "",
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pll_n=peripheral.get("pll_n", 32), pll_en=peripheral["pll_en"],
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pll_n=peripheral.get("pll_n", 32), pll_en=pll_en,
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sync_delay_seed=",\n \"sync_delay_seed\": \"eeprom_{}:{}\"".format(urukul_name, 64 + 4*i) if synchronization else "",
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io_update_delay=",\n \"io_update_delay\": \"eeprom_{}:{}\"".format(urukul_name, 64 + 4*i) if synchronization else "")
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elif dds == "ad9912":
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@ -320,7 +325,7 @@ class PeripheralManager:
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uchn=i,
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sw=",\n \"sw_device\": \"ttl_{name}_sw{uchn}\"".format(name=urukul_name, uchn=i) if len(peripheral["ports"]) > 1 else "",
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pll_vco=",\n \"pll_vco\": {}".format(pll_vco) if pll_vco is not None else "",
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pll_n=peripheral.get("pll_n", 8), pll_en=peripheral["pll_en"])
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pll_n=peripheral.get("pll_n", 8), pll_en=pll_en)
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else:
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raise ValueError
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return next(channel)
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