mirror of https://github.com/m-labs/artiq.git
runtime: enable ad9914 matched latency
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@ -77,18 +77,12 @@ void dds_init(long long int timestamp, int channel)
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#endif
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#ifdef DDS_AD9914
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/*
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* Enable cosine output (to match AD9858 behavior)
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* Enable DAC calibration
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* Leave SYNCLK enabled and PLL/divider disabled
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*/
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DDS_WRITE(DDS_CFR1L, 0x0008);
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DDS_WRITE(DDS_CFR1H, 0x0000);
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DDS_WRITE(DDS_CFR4H, 0x0105);
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DDS_WRITE(DDS_CFR1H, 0x0000); /* Enable cosine output */
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DDS_WRITE(DDS_CFR2L, 0x8900); /* Enable matched latency */
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DDS_WRITE(DDS_CFR4H, 0x0105); /* Enable DAC calibration */
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DDS_WRITE(DDS_FUD, 0);
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/* Disable DAC calibration */
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now += DURATION_DAC_CAL;
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DDS_WRITE(DDS_CFR4H, 0x0005);
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DDS_WRITE(DDS_CFR4H, 0x0005); /* Disable DAC calibration */
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DDS_WRITE(DDS_FUD, 0);
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#endif
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}
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@ -237,13 +237,13 @@ static void ddsinit(void)
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long long int t;
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brg_ddsreset();
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brg_ddswrite(DDS_CFR1L, 0x0008);
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brg_ddswrite(DDS_CFR1H, 0x0000);
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brg_ddswrite(DDS_CFR4H, 0x0105);
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brg_ddswrite(DDS_CFR1H, 0x0000); /* Enable cosine output */
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brg_ddswrite(DDS_CFR2L, 0x8900); /* Enable matched latency */
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brg_ddswrite(DDS_CFR4H, 0x0105); /* Enable DAC calibration */
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brg_ddswrite(DDS_FUD, 0);
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t = clock_get_ms();
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while(clock_get_ms() < t + 2);
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brg_ddswrite(DDS_CFR4H, 0x0005);
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brg_ddswrite(DDS_CFR4H, 0x0005); /* Disable DAC calibration */
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brg_ddsfud();
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}
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#endif
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