mirror of https://github.com/m-labs/artiq.git
gateware/spi: stubs
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@ -19,7 +19,7 @@ from misoc.targets.pipistrello import *
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from artiq.gateware.soc import AMPSoC
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from artiq.gateware import rtio, nist_qc1
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_spartan6, dds
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_spartan6, dds, spi
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from artiq import __artiq_dir__ as artiq_dir
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from artiq import __version__ as artiq_version
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@ -152,12 +152,12 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512,
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ofifo_depth=4))
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# ttl2 can run on a 8x serdes if xtrig is not used
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for i in range(15):
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# the last five ttls are used for SPI and a ClockGen
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for i in range(11):
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if i in (0, 1):
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phy = ttl_serdes_spartan6.Output_4X(platform.request("ttl", i),
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self.rtio_crg.rtiox4_stb)
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elif i in (2,):
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elif i in (2,): # ttl2 can run on a 8x serdes if xtrig is not used
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phy = ttl_serdes_spartan6.Output_8X(platform.request("ttl", i),
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self.rtio_crg.rtiox8_stb)
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else:
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@ -192,6 +192,20 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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ofifo_depth=512,
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ififo_depth=4))
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spi_pins = Record([("cs_n", 1), ("clk", 1), ("mosi", 1), ("miso", 1)])
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# cs_n can be multiple bits wide, one-hot
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# absence of miso indicates bidirectional mosi
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self.comb += [
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platform.request("ttl", 11).eq(spi_pins.cs_n),
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platform.request("ttl", 12).eq(spi_pins.clk),
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platform.request("ttl", 13).eq(spi_pins.mosi),
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spi_pins.miso.eq(platform.request("ttl", 14)),
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]
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phy = spi.SPIMaster(spi_pins)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ofifo_depth=4, ififo_depth=4))
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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