From fb35336389242f8b50bab0edfd52db785ae81257 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 30 Dec 2016 12:41:06 +0100 Subject: [PATCH] typo --- artiq/examples/phaser/repository/dac_setup.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/artiq/examples/phaser/repository/dac_setup.py b/artiq/examples/phaser/repository/dac_setup.py index 2364ff183..31c355dfb 100644 --- a/artiq/examples/phaser/repository/dac_setup.py +++ b/artiq/examples/phaser/repository/dac_setup.py @@ -302,7 +302,7 @@ class DACSetup(EnvExperiment): AD9154_SYNCMODE_SET(0x9) | AD9154_SYNCENABLE_SET(1) | AD9154_SYNCARM_SET(1) | AD9154_SYNCCLRSTKY_SET(0) | AD9154_SYNCCLRLAST_SET(0)) - self.busywait_us(1000) # ensure at leas one sysref edge + self.busywait_us(1000) # ensure at least one sysref edge if not AD9154_SYNC_LOCK_GET(self.ad9154.dac_read(AD9154_SYNC_STATUS)): raise ValueError("no sync lock") self.ad9154.dac_write(AD9154_XBAR_LN_0_1,