mirror of https://github.com/m-labs/artiq.git
rtio/sed: remove VCD fine in unittest
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@ -82,7 +82,7 @@ def simulate(input_events):
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yield
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run_simulation(dut, {"sys": [gen(), monitor()]},
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{"sys": 5, "rio": 5, "rio_phy": 5}, vcd_name="foo.vcd")
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{"sys": 5, "rio": 5, "rio_phy": 5})
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return output
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