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artiq
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satman: use new SYSREF code

This commit is contained in:
Sebastien Bourdeauducq 2018-07-26 16:26:57 +08:00
parent 32c95ac034
commit f8c17528e7
1 changed files with 12 additions and 8 deletions
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20
artiq/firmware/satman/main.rs
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@ -249,10 +249,6 @@ fn drtio_link_rx_up() -> bool {
} }
const SIPHASER_PHASE: u16 = 32; const SIPHASER_PHASE: u16 = 32;
#[cfg(has_ad9154)]
const SYSREF_PHASE_FPGA: u16 = 54;
#[cfg(has_ad9154)]
const SYSREF_PHASE_DAC: u16 = 61;
#[no_mangle] #[no_mangle]
pub extern fn main() -> i32 { pub extern fn main() -> i32 {
@ -292,7 +288,14 @@ pub extern fn main() -> i32 {
#[cfg(has_ad9154)] #[cfg(has_ad9154)]
{ {
if !ad9154_initialized { if !ad9154_initialized {
board_artiq::ad9154::init(SYSREF_PHASE_FPGA, SYSREF_PHASE_DAC); board_artiq::ad9154::jesd_unreset();
board_artiq::ad9154::init();
if let Err(e) = board_artiq::jesd204sync::sysref_auto_rtio_align(1) {
error!("failed to align SYSREF at FPGA: {}", e);
}
if let Err(e) = board_artiq::jesd204sync::sysref_auto_dac_align() {
error!("failed to align SYSREF at DAC: {}", e);
}
ad9154_initialized = true; ad9154_initialized = true;
} }
} }
@ -306,9 +309,10 @@ pub extern fn main() -> i32 {
{ {
if drtio_tsc_loaded() { if drtio_tsc_loaded() {
// Expected alignment: 1 RTIO clock period // Expected alignment: 1 RTIO clock period
hmc830_7043::hmc7043::sysref_rtio_align( if let Err(e) = board_artiq::jesd204sync::sysref_auto_rtio_align(
SYSREF_PHASE_FPGA, hmc830_7043::hmc7043::FPGA_CLK_DIV) {
hmc830_7043::hmc7043::FPGA_CLK_DIV); error!("failed to align SYSREF at FPGA: {}", e);
}
} }
} }
} }