From f8a9dd930b0a42ac8c98c340c9fa4b8fc4467993 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 15 May 2018 23:51:14 +0200 Subject: [PATCH] serwb/genphy: add device parameter (not used here, but this way all the phys share the same parameters), scrambling is also now always enabled. --- artiq/gateware/serwb/genphy.py | 13 +++---------- artiq/gateware/targets/sayma_amc.py | 2 +- artiq/gateware/targets/sayma_rtm.py | 2 +- 3 files changed, 5 insertions(+), 12 deletions(-) diff --git a/artiq/gateware/serwb/genphy.py b/artiq/gateware/serwb/genphy.py index 07ab731ad..3c385b0d3 100644 --- a/artiq/gateware/serwb/genphy.py +++ b/artiq/gateware/serwb/genphy.py @@ -317,8 +317,6 @@ class _SerdesControl(Module, AutoCSR): self.bitslip = CSRStatus(6) - self.scrambling_enable = CSRStorage() - self.prbs_error = Signal() self.prbs_start = CSR() self.prbs_cycles = CSRStorage(32) @@ -369,7 +367,7 @@ class _SerdesControl(Module, AutoCSR): class SERWBPHY(Module, AutoCSR): - def __init__(self, pads, mode="master", init_timeout=2**16): + def __init__(self, device, pads, mode="master", init_timeout=2**16): self.sink = sink = stream.Endpoint([("data", 32)]) self.source = source = stream.Endpoint([("data", 32)]) assert mode in ["master", "slave"] @@ -381,13 +379,8 @@ class SERWBPHY(Module, AutoCSR): self.submodules.control = _SerdesControl(self.serdes, self.init, mode) # scrambling - scrambler = Scrambler() - descrambler = Descrambler() - self.submodules += scrambler, descrambler - self.comb += [ - scrambler.enable.eq(self.control.scrambling_enable.storage), - descrambler.enable.eq(self.control.scrambling_enable.storage) - ] + self.submodules.scrambler = scrambler = Scrambler() + self.submodules.descrambler = descrambler = Descrambler() # tx dataflow self.comb += \ diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index fe98c0fac..09d686c3b 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -174,7 +174,7 @@ class Standalone(MiniSoC, AMPSoC): # AMC/RTM serwb serwb_pads = platform.request("amc_rtm_serwb") - serwb_phy_amc = serwb.genphy.SERWBPHY(serwb_pads, mode="master") + serwb_phy_amc = serwb.genphy.SERWBPHY(platform.device, serwb_pads, mode="master") self.submodules.serwb_phy_amc = serwb_phy_amc self.csr_devices.append("serwb_phy_amc") diff --git a/artiq/gateware/targets/sayma_rtm.py b/artiq/gateware/targets/sayma_rtm.py index 16c55c619..66855e4d8 100755 --- a/artiq/gateware/targets/sayma_rtm.py +++ b/artiq/gateware/targets/sayma_rtm.py @@ -151,7 +151,7 @@ class SaymaRTM(Module): # AMC/RTM serwb serwb_pads = platform.request("amc_rtm_serwb") platform.add_period_constraint(serwb_pads.clk_p, 8.) - serwb_phy_rtm = serwb.genphy.SERWBPHY(serwb_pads, mode="slave") + serwb_phy_rtm = serwb.genphy.SERWBPHY(platform.device, serwb_pads, mode="slave") self.submodules.serwb_phy_rtm = serwb_phy_rtm self.comb += [ self.crg.serwb_refclk.eq(serwb_phy_rtm.serdes.clocking.refclk),