From f8a7e278b84dcc18fb29749de7fa1d2839d3d6e0 Mon Sep 17 00:00:00 2001 From: Garrett Date: Tue, 12 Nov 2019 11:03:00 -0600 Subject: [PATCH] removed OSK-related changes in AD9910, to be included in a separate branch. --- artiq/coredevice/ad9910.py | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/artiq/coredevice/ad9910.py b/artiq/coredevice/ad9910.py index baa77b50d..a93242455 100644 --- a/artiq/coredevice/ad9910.py +++ b/artiq/coredevice/ad9910.py @@ -345,8 +345,7 @@ class AD9910: @kernel def set_cfr1(self, power_down=0b0000, phase_autoclear=0, drg_load_lrr=0, drg_autoclear=0, - internal_profile=0, ram_destination=0, ram_enable=0, - manual_osk_external=0, osk_enable=0, select_auto_osk=0): + internal_profile=0, ram_destination=0, ram_enable=0): """Set CFR1. See the AD9910 datasheet for parameter meanings. This method does not pulse IO_UPDATE. @@ -360,20 +359,14 @@ class AD9910: (:const:`RAM_DEST_FTW`, :const:`RAM_DEST_POW`, :const:`RAM_DEST_ASF`, :const:`RAM_DEST_POWASF`). :param ram_enable: RAM mode enable. - :param manual_osk_external: Enable OSK pin control in manual OSK mode. - :param osk_enable: Enable OSK mode. - :param select_auto_osk: Select manual or automatic OSK mode. """ self.write32(_AD9910_REG_CFR1, (ram_enable << 31) | (ram_destination << 29) | - (manual_osk_external << 23) | (internal_profile << 17) | (drg_load_lrr << 15) | (drg_autoclear << 14) | (phase_autoclear << 13) | - (osk_enable << 9) | - (select_auto_osk << 8) | (power_down << 4) | 2) # SDIO input only, MSB first