From f77a75ab1728b452856337a1d83200f04b1190b1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Wed, 14 Nov 2018 07:41:24 +0000 Subject: [PATCH] test_ad9910: robustify w.r.t. profile synchronization MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Robert Jördens --- artiq/test/coredevice/test_ad9910.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/artiq/test/coredevice/test_ad9910.py b/artiq/test/coredevice/test_ad9910.py index fe5ad6a66..b5294e80e 100644 --- a/artiq/test/coredevice/test_ad9910.py +++ b/artiq/test/coredevice/test_ad9910.py @@ -144,6 +144,10 @@ class AD9910Exp(EnvExperiment): ftw = [0] * 8 for i in range(8): self.dev.cpld.set_profile(i) + # If PROFILE is not alligned to SYNC_CLK a multi-bit change + # doesn't transfer cleanly. Use IO_UPDATE to load the profile + # again. + self.dev.cpld.io_update.pulse_mu(8) ftw[i] = self.dev.read32(_AD9910_REG_FTW) delay(100*us) self.set_dataset("ftw", ftw)