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drtio: 8-bit address

This commit is contained in:
Sebastien Bourdeauducq 2018-11-08 18:36:20 +08:00
parent 8caea0e6d3
commit f74dda639f
3 changed files with 7 additions and 7 deletions
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8
artiq/gateware/drtio/rt_packet_master.py
View File

@ -27,7 +27,7 @@ class RTPacketMaster(Module):
self.sr_notwrite = Signal() self.sr_notwrite = Signal()
self.sr_timestamp = Signal(64) self.sr_timestamp = Signal(64)
self.sr_chan_sel = Signal(24) self.sr_chan_sel = Signal(24)
self.sr_address = Signal(16) self.sr_address = Signal(8)
self.sr_data = Signal(512) self.sr_data = Signal(512)
# buffer space reply interface # buffer space reply interface
@ -85,12 +85,12 @@ class RTPacketMaster(Module):
# Write FIFO and extra data count # Write FIFO and extra data count
sr_fifo = ClockDomainsRenamer({"write": "sys", "read": "rtio"})( sr_fifo = ClockDomainsRenamer({"write": "sys", "read": "rtio"})(
AsyncFIFO(1+64+24+16+512, sr_fifo_depth)) AsyncFIFO(1+64+24+8+512, sr_fifo_depth))
self.submodules += sr_fifo self.submodules += sr_fifo
sr_notwrite_d = Signal() sr_notwrite_d = Signal()
sr_timestamp_d = Signal(64) sr_timestamp_d = Signal(64)
sr_chan_sel_d = Signal(24) sr_chan_sel_d = Signal(24)
sr_address_d = Signal(16) sr_address_d = Signal(8)
sr_data_d = Signal(512) sr_data_d = Signal(512)
self.comb += [ self.comb += [
sr_fifo.we.eq(self.sr_stb), sr_fifo.we.eq(self.sr_stb),
@ -115,7 +115,7 @@ class RTPacketMaster(Module):
sr_notwrite = Signal() sr_notwrite = Signal()
sr_timestamp = Signal(64) sr_timestamp = Signal(64)
sr_chan_sel = Signal(24) sr_chan_sel = Signal(24)
sr_address = Signal(16) sr_address = Signal(8)
sr_extra_data_cnt = Signal(8) sr_extra_data_cnt = Signal(8)
sr_data = Signal(512) sr_data = Signal(512)

4
artiq/gateware/drtio/rt_packet_repeater.py
View File

@ -58,7 +58,7 @@ class RTPacketRepeater(Module):
cb0_cmd = Signal(2) cb0_cmd = Signal(2)
cb0_timestamp = Signal(64) cb0_timestamp = Signal(64)
cb0_chan_sel = Signal(24) cb0_chan_sel = Signal(24)
cb0_o_address = Signal(16) cb0_o_address = Signal(8)
cb0_o_data = Signal(512) cb0_o_data = Signal(512)
self.sync.rtio += [ self.sync.rtio += [
If(self.reset | cb0_ack, If(self.reset | cb0_ack,
@ -89,7 +89,7 @@ class RTPacketRepeater(Module):
cb_cmd = Signal(2) cb_cmd = Signal(2)
cb_timestamp = Signal(64) cb_timestamp = Signal(64)
cb_chan_sel = Signal(24) cb_chan_sel = Signal(24)
cb_o_address = Signal(16) cb_o_address = Signal(8)
cb_o_data = Signal(512) cb_o_data = Signal(512)
self.sync.rtio += [ self.sync.rtio += [
If(self.reset | cb_ack, If(self.reset | cb_ack,

2
artiq/gateware/drtio/rt_serializer.py
View File

@ -50,7 +50,7 @@ def get_m2s_layouts(alignment):
plm.add_type("write", ("timestamp", 64), plm.add_type("write", ("timestamp", 64),
("chan_sel", 24), ("chan_sel", 24),
("address", 16), ("address", 8),
("extra_data_cnt", 8), ("extra_data_cnt", 8),
("short_data", short_data_len)) ("short_data", short_data_len))
plm.add_type("buffer_space_request", ("destination", 8)) plm.add_type("buffer_space_request", ("destination", 8))