diff --git a/artiq/gateware/suservo/adc_ser.py b/artiq/gateware/suservo/adc_ser.py
index c010cd3b9..f0006d927 100644
--- a/artiq/gateware/suservo/adc_ser.py
+++ b/artiq/gateware/suservo/adc_ser.py
@@ -118,18 +118,7 @@ class ADC(Module, DiffMixin):
             sck_en_ret = pads.sck_en_ret
         except AttributeError:
             sck_en_ret = 1
-        self.clock_domains.cd_ret = ClockDomain("ret", reset_less=True)
-        clkout = self._diff(pads, "clkout")
-        clkout_fabric = Signal()
-        clkout_io = Signal()
-        self.specials += [
-                Instance("BUFH", i_I=clkout, o_O=clkout_fabric),
-                Instance("BUFIO", i_I=clkout, o_O=clkout_io)
-        ]
-        self.comb += [
-                # falling clkout makes two bits available
-                self.cd_ret.clk.eq(~clkout_fabric)
-        ]
+        self.clkout_io = Signal()
         k = p.channels//p.lanes
         assert 2*t_read == k*p.width
         for i, sdo in enumerate(sdo):
@@ -137,7 +126,7 @@ class ADC(Module, DiffMixin):
             sdo_sr1 = Signal(t_read - 1)
             sdo_ddr = Signal(2)
             self.specials += io.DDRInput(sdo, sdo_ddr[1], sdo_ddr[0],
-                    ~clkout_io)
+                    ~self.clkout_io)
             self.sync.ret += [
                     If(self.reading & sck_en_ret,
                         sdo_sr0.eq(Cat(sdo_ddr[0], sdo_sr0)),
diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py
index a7b996512..de3aad6c8 100755
--- a/artiq/gateware/targets/kasli.py
+++ b/artiq/gateware/targets/kasli.py
@@ -8,7 +8,7 @@ from migen.genlib.cdc import MultiReg
 from migen.build.generic_platform import *
 from migen.build.xilinx.vivado import XilinxVivadoToolchain
 from migen.build.xilinx.ise import XilinxISEToolchain
-from migen.genlib.io import DifferentialOutput
+from migen.genlib.io import DifferentialOutput, DifferentialInput
 
 from misoc.interconnect.csr import *
 from misoc.cores import gpio
@@ -540,6 +540,19 @@ class SUServo(_StandaloneBase):
         su = ClockDomainsRenamer({"sys": "rio_phy"})(su)
         self.submodules += sampler_pads, urukul_pads, su
 
+        self.clock_domains.cd_ret = ClockDomain("ret", reset_less=True)
+        clkout = Signal()
+        clkout_fabric = Signal()
+        self.specials += [
+                DifferentialInput(pads.clkout_p, pads.clkout_n, clkout),
+                Instance("BUFH", i_I=clkout, o_O=clkout_fabric),
+                Instance("BUFIO", i_I=clkout, o_O=su.adc.clkout_io)
+        ]
+        self.comb += [
+                # falling clkout makes two bits available
+                self.cd_ret.clk.eq(~clkout_fabric)
+        ]
+
         ctrls = [rtservo.RTServoCtrl(ctrl) for ctrl in su.iir.ctrl]
         self.submodules += ctrls
         rtio_channels.extend(rtio.Channel.from_phy(ctrl) for ctrl in ctrls)
diff --git a/artiq/gateware/test/suservo/test_adc.py b/artiq/gateware/test/suservo/test_adc.py
index 2dbcd6342..3fc11352f 100644
--- a/artiq/gateware/test/suservo/test_adc.py
+++ b/artiq/gateware/test/suservo/test_adc.py
@@ -75,6 +75,12 @@ class TB(Module):
         cd_adc = ClockDomain("adc", reset_less=True)
         self.clock_domains += cd_adc
 
+        self.clock_domains.cd_ret = ClockDomain("ret", reset_less=True)
+        self.comb += [
+                # falling clkout makes two bits available
+                self.cd_ret.clk.eq(~self.clkout)
+        ]
+
         self.sdo = []
         self.data = [Signal((p.width, True), reset_less=True)
                 for i in range(p.channels)]
@@ -124,6 +130,7 @@ def main():
     tb = TB(params)
     adc = ADC(tb, params)
     tb.submodules += adc
+    tb.comb += adc.clkout_io.eq(tb.clkout)
 
     def run(tb):
         dut = adc
diff --git a/artiq/gateware/test/suservo/test_servo.py b/artiq/gateware/test/suservo/test_servo.py
index c8b43349e..a33c379a7 100644
--- a/artiq/gateware/test/suservo/test_servo.py
+++ b/artiq/gateware/test/suservo/test_servo.py
@@ -23,6 +23,7 @@ class ServoSim(servo.Servo):
 
         servo.Servo.__init__(self, self.adc_tb, self.dds_tb,
                 adc_p, iir_p, dds_p)
+        self.adc_tb.comb += self.adc.clkout_io.eq(self.adc_tb.clkout)
 
     def test(self):
         assert (yield self.done)