wrpll.thls: fix make

2020-10-05 22:55:20 +01:00 · 2020-10-05 22:55:20 +01:00 · f6f6045f1a
parent b44b870452
commit f6f6045f1a
1 changed files with 4 additions and 4 deletions
--- a/artiq/gateware/drtio/wrpll/thls.py
+++ b/artiq/gateware/drtio/wrpll/thls.py
@ -591,7 +591,7 @@ class ProcessorImpl(Module):

 def make(function, **kwargs):
    proc = Processor(**kwargs)
-    cp = compile(proc, simple_test)
+    cp = compile(proc, function)
    cp.dimension_processor()
    return proc.implement(cp.encode(), cp.data)