From f68d5cbd736ee161d47114e33902aad8e9fe9af0 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 27 Jul 2015 01:52:47 +0800 Subject: [PATCH] rtio: forward rtio domain reset to rio and rio_phy domains --- artiq/gateware/rtio/core.py | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/artiq/gateware/rtio/core.py b/artiq/gateware/rtio/core.py index b4fedcf88..38446604e 100644 --- a/artiq/gateware/rtio/core.py +++ b/artiq/gateware/rtio/core.py @@ -329,11 +329,15 @@ class RTIO(Module): self.cd_rsys.rst.eq(self.kcsrs.reset.storage) ] self.comb += self.cd_rio.clk.eq(ClockSignal("rtio")) - self.specials += AsyncResetSynchronizer(self.cd_rio, - self.kcsrs.reset.storage) + self.specials += AsyncResetSynchronizer( + self.cd_rio, + self.kcsrs.reset.storage | ResetSignal("rtio", + allow_resetless=True)) self.comb += self.cd_rio_phy.clk.eq(ClockSignal("rtio")) - self.specials += AsyncResetSynchronizer(self.cd_rio_phy, - self.kcsrs.reset_phy.storage) + self.specials += AsyncResetSynchronizer( + self.cd_rio_phy, + self.kcsrs.reset_phy.storage | ResetSignal("rtio", + allow_resetless=True)) # Managers self.submodules.counter = _RTIOCounter(full_ts_width - fine_ts_width)