diff --git a/artiq/gateware/targets/kc705_drtio_master.py b/artiq/gateware/targets/kc705_drtio_master.py
index c2e22cb93..8ee6e6952 100755
--- a/artiq/gateware/targets/kc705_drtio_master.py
+++ b/artiq/gateware/targets/kc705_drtio_master.py
@@ -53,7 +53,7 @@ class Master(MiniSoC, AMPSoC):
         elif cfg == "sawg_3g":
             # 3Gb link, 150MHz RTIO clock
             # with SAWG on local RTIO and AD9154-FMC-EBZ
-            platform.register_extension(ad9154_fmc_ebz)
+            platform.add_extension(ad9154_fmc_ebz)
             self.submodules.transceiver = gtx_7series.GTX_3G(
                 clock_pads=platform.request("ad9154_refclk"),
                 tx_pads=tx_pads,
diff --git a/artiq/gateware/targets/kc705_drtio_satellite.py b/artiq/gateware/targets/kc705_drtio_satellite.py
index 681248453..2bda7e9fb 100755
--- a/artiq/gateware/targets/kc705_drtio_satellite.py
+++ b/artiq/gateware/targets/kc705_drtio_satellite.py
@@ -169,7 +169,7 @@ class Satellite(BaseSoC):
         elif cfg == "sawg_3g":
             # 3Gb link, 150MHz RTIO clock
             # with SAWG on local RTIO and AD9154-FMC-EBZ
-            platform.register_extension(ad9154_fmc_ebz)
+            platform.add_extension(ad9154_fmc_ebz)
             self.submodules.transceiver = gtx_7series.GTX_3G(
                 clock_pads=platform.request("ad9154_refclk"),
                 tx_pads=tx_pads,