mirror of https://github.com/m-labs/artiq.git
rtio: undo _RelaxedAsyncResetSynchronizer
This commit is contained in:
parent
6fad15c532
commit
f520d4a768
|
@ -284,18 +284,6 @@ class LogChannel:
|
||||||
self.overrides = []
|
self.overrides = []
|
||||||
|
|
||||||
|
|
||||||
class _RelaxedAsyncResetSynchronizer(Module):
|
|
||||||
def __init__(self, cd, async_reset):
|
|
||||||
self.clock_domains.cd_rst = ClockDomain()
|
|
||||||
rst_fan = Signal(reset_less=True)
|
|
||||||
self.specials += AsyncResetSynchronizer(self.cd_rst, async_reset)
|
|
||||||
self.comb += [
|
|
||||||
self.cd_rst.clk.eq(cd.clk),
|
|
||||||
cd.rst.eq(rst_fan),
|
|
||||||
]
|
|
||||||
self.sync.rst += rst_fan.eq(self.cd_rst.rst)
|
|
||||||
|
|
||||||
|
|
||||||
class Core(Module, AutoCSR):
|
class Core(Module, AutoCSR):
|
||||||
def __init__(self, channels, fine_ts_width=None, guard_io_cycles=20):
|
def __init__(self, channels, fine_ts_width=None, guard_io_cycles=20):
|
||||||
if fine_ts_width is None:
|
if fine_ts_width is None:
|
||||||
|
@ -336,10 +324,8 @@ class Core(Module, AutoCSR):
|
||||||
self.cd_rio.clk.eq(ClockSignal("rtio")),
|
self.cd_rio.clk.eq(ClockSignal("rtio")),
|
||||||
self.cd_rio_phy.clk.eq(ClockSignal("rtio"))
|
self.cd_rio_phy.clk.eq(ClockSignal("rtio"))
|
||||||
]
|
]
|
||||||
self.submodules.rars_rio = _RelaxedAsyncResetSynchronizer(
|
self.specials += AsyncResetSynchronizer(self.cd_rio, cmd_reset)
|
||||||
self.cd_rio, cmd_reset)
|
self.specials += AsyncResetSynchronizer(self.cd_rio_phy, cmd_reset_phy)
|
||||||
self.submodules.rars_rio_phy = _RelaxedAsyncResetSynchronizer(
|
|
||||||
self.cd_rio_phy, cmd_reset_phy)
|
|
||||||
|
|
||||||
# Managers
|
# Managers
|
||||||
self.submodules.counter = RTIOCounter(len(self.cri.timestamp) - fine_ts_width)
|
self.submodules.counter = RTIOCounter(len(self.cri.timestamp) - fine_ts_width)
|
||||||
|
|
Loading…
Reference in New Issue