mirror of
https://github.com/m-labs/artiq.git
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Merge branch 'master' of github.com:m-labs/artiq
This commit is contained in:
commit
f4f95d330b
@ -1,12 +1,12 @@
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from artiq.coredevice import exceptions, dds, spi
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from artiq.coredevice import exceptions, dds, spi
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from artiq.coredevice.exceptions import (RTIOUnderflow, RTIOSequenceError,
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from artiq.coredevice.exceptions import (RTIOUnderflow, RTIOSequenceError,
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RTIOCollision, RTIOOverflow,
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RTIOCollision, RTIOOverflow, RTIOBusy,
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DDSBatchError, CacheError)
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DDSBatchError, CacheError)
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from artiq.coredevice.dds import (PHASE_MODE_CONTINUOUS, PHASE_MODE_ABSOLUTE,
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from artiq.coredevice.dds import (PHASE_MODE_CONTINUOUS, PHASE_MODE_ABSOLUTE,
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PHASE_MODE_TRACKING)
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PHASE_MODE_TRACKING)
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__all__ = []
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__all__ = []
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__all__ += ["RTIOUnderflow", "RTIOSequenceError", "RTIOCollision",
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__all__ += ["RTIOUnderflow", "RTIOSequenceError", "RTIOCollision",
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"RTIOOverflow", "DDSBatchError", "CacheError"]
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"RTIOOverflow", "RTIOBusy", "DDSBatchError", "CacheError"]
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__all__ += ["PHASE_MODE_CONTINUOUS", "PHASE_MODE_ABSOLUTE",
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__all__ += ["PHASE_MODE_CONTINUOUS", "PHASE_MODE_ABSOLUTE",
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"PHASE_MODE_TRACKING"]
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"PHASE_MODE_TRACKING"]
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@ -82,7 +82,7 @@ class _DDSGeneric:
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:param bus: name of the DDS bus device that this DDS is connected to.
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:param bus: name of the DDS bus device that this DDS is connected to.
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:param channel: channel number of the DDS device to control.
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:param channel: channel number of the DDS device to control.
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"""
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"""
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def __init__(self, dmgr, sysclk, bus_channel, channel, core_dds_device="core_dds"):
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def __init__(self, dmgr, bus_channel, channel, core_dds_device="core_dds"):
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self.core_dds = dmgr.get(core_dds_device)
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self.core_dds = dmgr.get(core_dds_device)
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self.core = self.core_dds.core
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self.core = self.core_dds.core
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self.bus_channel = bus_channel
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self.bus_channel = bus_channel
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@ -98,6 +98,18 @@ class RTIOCollision(Exception):
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"""
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"""
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artiq_builtin = True
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artiq_builtin = True
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class RTIOBusy(Exception):
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"""Raised when at least one output event could not be executed because
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the given channel was already busy executing a previous event.
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This exception is raised late: after the error condition occurred. More
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specifically it is raised on submitting an event on the same channel after
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the execution of the faulty event was attempted.
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The offending event was discarded.
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"""
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artiq_builtin = True
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class RTIOOverflow(Exception):
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class RTIOOverflow(Exception):
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"""Raised when at least one event could not be registered into the RTIO
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"""Raised when at least one event could not be registered into the RTIO
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input FIFO because it was full (CPU not reading fast enough).
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input FIFO because it was full (CPU not reading fast enough).
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@ -1,5 +1,5 @@
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from artiq.language.core import (kernel, portable, seconds_to_mu, now_mu,
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from artiq.language.core import (kernel, portable, seconds_to_mu, now_mu,
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delay_mu, int)
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delay_mu, int, mu_to_seconds)
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from artiq.language.units import MHz
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from artiq.language.units import MHz
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from artiq.coredevice.rtio import rtio_output, rtio_input_data
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from artiq.coredevice.rtio import rtio_output, rtio_input_data
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@ -58,7 +58,7 @@ class SPIMaster:
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@portable
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@portable
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def frequency_to_div(self, f):
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def frequency_to_div(self, f):
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return int(1/(f*self.ref_period)) + 1
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return int(1/(f*mu_to_seconds(self.ref_period_mu))) + 1
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@kernel
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@kernel
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def set_config(self, flags=0, write_freq=20*MHz, read_freq=20*MHz):
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def set_config(self, flags=0, write_freq=20*MHz, read_freq=20*MHz):
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@ -54,6 +54,26 @@ class _RTIOCounter(Module):
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self.comb += gt.i.eq(self.value_rtio), self.value_sys.eq(gt.o)
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self.comb += gt.i.eq(self.value_rtio), self.value_sys.eq(gt.o)
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class _BlindTransfer(Module):
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def __init__(self):
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self.i = Signal()
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self.o = Signal()
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ps = PulseSynchronizer("rio", "rsys")
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ps_ack = PulseSynchronizer("rsys", "rio")
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self.submodules += ps, ps_ack
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blind = Signal()
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self.sync.rio += [
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If(self.i, blind.eq(1)),
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If(ps_ack.o, blind.eq(0))
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]
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self.comb += [
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ps.i.eq(self.i & ~blind),
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ps_ack.i.eq(ps.o),
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self.o.eq(ps.o)
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]
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# CHOOSING A GUARD TIME
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# CHOOSING A GUARD TIME
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#
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#
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# The buffer must be transferred to the FIFO soon enough to account for:
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# The buffer must be transferred to the FIFO soon enough to account for:
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@ -104,6 +124,7 @@ class _OutputManager(Module):
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self.underflow = Signal() # valid 1 cycle after we, pulsed
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self.underflow = Signal() # valid 1 cycle after we, pulsed
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self.sequence_error = Signal()
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self.sequence_error = Signal()
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self.collision = Signal()
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self.collision = Signal()
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self.busy = Signal() # pulsed
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# # #
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# # #
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@ -132,11 +153,10 @@ class _OutputManager(Module):
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# Note: replace may be asserted at the same time as collision
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# Note: replace may be asserted at the same time as collision
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# when addresses are different. In that case, it is a collision.
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# when addresses are different. In that case, it is a collision.
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self.sync.rsys += replace.eq(self.ev.timestamp == buf.timestamp)
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self.sync.rsys += replace.eq(self.ev.timestamp == buf.timestamp)
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self.sync.rsys += \
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# Detect sequence errors on coarse timestamps only
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# Detect sequence errors on coarse timestamps only
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# so that they are mutually exclusive with collision errors.
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# so that they are mutually exclusive with collision errors.
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sequence_error.eq(self.ev.timestamp[fine_ts_width:]
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self.sync.rsys += sequence_error.eq(self.ev.timestamp[fine_ts_width:] <
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< buf.timestamp[fine_ts_width:])
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buf.timestamp[fine_ts_width:])
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if interface.enable_replace:
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if interface.enable_replace:
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if hasattr(self.ev, "a"):
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if hasattr(self.ev, "a"):
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different_addresses = self.ev.a != buf.a
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different_addresses = self.ev.a != buf.a
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@ -203,12 +223,19 @@ class _OutputManager(Module):
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self.comb += fifo.re.eq(fifo.readable & (~dout_stb | dout_ack))
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self.comb += fifo.re.eq(fifo.readable & (~dout_stb | dout_ack))
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# FIFO read through buffer
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# FIFO read through buffer
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# TODO: report error on stb & busy
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self.comb += [
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self.comb += [
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dout_ack.eq(
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dout_ack.eq(
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dout.timestamp[fine_ts_width:] == counter.value_rtio),
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dout.timestamp[fine_ts_width:] == counter.value_rtio),
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interface.stb.eq(dout_stb & dout_ack)
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interface.stb.eq(dout_stb & dout_ack)
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]
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]
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busy_transfer = _BlindTransfer()
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self.submodules += busy_transfer
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self.comb += [
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busy_transfer.i.eq(interface.stb & interface.busy),
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self.busy.eq(busy_transfer.o),
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]
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if data_width:
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if data_width:
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self.comb += interface.data.eq(dout.data)
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self.comb += interface.data.eq(dout.data)
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if address_width:
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if address_width:
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@ -231,7 +258,7 @@ class _InputManager(Module):
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self.readable = Signal()
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self.readable = Signal()
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self.re = Signal()
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self.re = Signal()
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self.overflow = Signal() # pulsed
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self.overflow = Signal() # pulsed
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# # #
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# # #
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@ -264,18 +291,11 @@ class _InputManager(Module):
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fifo.re.eq(self.re)
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fifo.re.eq(self.re)
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]
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]
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overflow_sync = PulseSynchronizer("rio", "rsys")
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overflow_transfer = _BlindTransfer()
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overflow_ack_sync = PulseSynchronizer("rsys", "rio")
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self.submodules += overflow_transfer
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self.submodules += overflow_sync, overflow_ack_sync
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overflow_blind = Signal()
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self.comb += overflow_sync.i.eq(fifo.we & ~fifo.writable & ~overflow_blind)
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self.sync.rio += [
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If(fifo.we & ~fifo.writable, overflow_blind.eq(1)),
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If(overflow_ack_sync.o, overflow_blind.eq(0))
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]
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self.comb += [
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self.comb += [
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overflow_ack_sync.i.eq(overflow_sync.o),
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overflow_transfer.i.eq(fifo.we & ~fifo.writable),
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self.overflow.eq(overflow_sync.o)
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self.overflow.eq(overflow_transfer.o),
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]
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]
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@ -321,10 +341,11 @@ class _KernelCSRs(AutoCSR):
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self.o_address = CSRStorage(address_width)
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self.o_address = CSRStorage(address_width)
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self.o_timestamp = CSRStorage(full_ts_width)
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self.o_timestamp = CSRStorage(full_ts_width)
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self.o_we = CSR()
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self.o_we = CSR()
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self.o_status = CSRStatus(4)
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self.o_status = CSRStatus(5)
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self.o_underflow_reset = CSR()
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self.o_underflow_reset = CSR()
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self.o_sequence_error_reset = CSR()
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self.o_sequence_error_reset = CSR()
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self.o_collision_reset = CSR()
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self.o_collision_reset = CSR()
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self.o_busy_reset = CSR()
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if data_width:
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if data_width:
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self.i_data = CSRStatus(data_width)
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self.i_data = CSRStatus(data_width)
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@ -412,6 +433,7 @@ class RTIO(Module):
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underflow = Signal()
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underflow = Signal()
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sequence_error = Signal()
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sequence_error = Signal()
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collision = Signal()
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collision = Signal()
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busy = Signal()
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self.sync.rsys += [
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self.sync.rsys += [
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If(selected & self.kcsrs.o_underflow_reset.re,
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If(selected & self.kcsrs.o_underflow_reset.re,
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underflow.eq(0)),
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underflow.eq(0)),
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@ -419,14 +441,18 @@ class RTIO(Module):
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sequence_error.eq(0)),
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sequence_error.eq(0)),
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If(selected & self.kcsrs.o_collision_reset.re,
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If(selected & self.kcsrs.o_collision_reset.re,
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collision.eq(0)),
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collision.eq(0)),
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If(selected & self.kcsrs.o_busy_reset.re,
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busy.eq(0)),
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If(o_manager.underflow, underflow.eq(1)),
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If(o_manager.underflow, underflow.eq(1)),
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If(o_manager.sequence_error, sequence_error.eq(1)),
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If(o_manager.sequence_error, sequence_error.eq(1)),
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If(o_manager.collision, collision.eq(1))
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If(o_manager.collision, collision.eq(1)),
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If(o_manager.busy, busy.eq(1))
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]
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]
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o_statuses.append(Cat(~o_manager.writable,
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o_statuses.append(Cat(~o_manager.writable,
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underflow,
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underflow,
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sequence_error,
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sequence_error,
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collision))
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collision,
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busy))
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if channel.interface.i is not None:
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if channel.interface.i is not None:
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i_manager = _InputManager(channel.interface.i, self.counter,
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i_manager = _InputManager(channel.interface.i, self.counter,
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@ -39,6 +39,12 @@ static void rtio_process_exceptional_status(
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"RTIO collision at {0} mu, channel {1}",
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"RTIO collision at {0} mu, channel {1}",
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timestamp, channel, 0);
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timestamp, channel, 0);
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}
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}
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if(status & RTIO_O_STATUS_BUSY) {
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rtio_o_busy_reset_write(1);
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artiq_raise_from_c("RTIOBusy",
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"RTIO busy on channel {0}",
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channel, 0, 0);
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}
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}
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}
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@ -7,6 +7,7 @@
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#define RTIO_O_STATUS_UNDERFLOW 2
|
#define RTIO_O_STATUS_UNDERFLOW 2
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#define RTIO_O_STATUS_SEQUENCE_ERROR 4
|
#define RTIO_O_STATUS_SEQUENCE_ERROR 4
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#define RTIO_O_STATUS_COLLISION 8
|
#define RTIO_O_STATUS_COLLISION 8
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#define RTIO_O_STATUS_BUSY 16
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#define RTIO_I_STATUS_EMPTY 1
|
#define RTIO_I_STATUS_EMPTY 1
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#define RTIO_I_STATUS_OVERFLOW 2
|
#define RTIO_I_STATUS_OVERFLOW 2
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|
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|
45
artiq/test/coredevice/test_spi.py
Normal file
45
artiq/test/coredevice/test_spi.py
Normal file
@ -0,0 +1,45 @@
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|
from artiq.experiment import *
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|
from artiq.test.hardware_testbench import ExperimentCase
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|
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|
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|
class Collision(EnvExperiment):
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|
def build(self):
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|
self.setattr_device("core")
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|
self.setattr_device("spi0")
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|
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|
@kernel
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|
def run(self):
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|
self.core.break_realtime()
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t = now_mu()
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self.spi0.set_config_mu()
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at_mu(t)
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self.spi0.set_config_mu()
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|
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|
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|
class Busy(EnvExperiment):
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|
def build(self):
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|
self.setattr_device("core")
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|
self.setattr_device("spi0")
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|
self.setattr_device("led")
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|
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|
@kernel
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|
def run(self):
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|
self.core.break_realtime()
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|
t = now_mu()
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|
self.spi0.set_config_mu()
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|
at_mu(t + self.spi0.ref_period_mu)
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|
self.spi0.set_config_mu() # causes the error
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|
self.led.on()
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|
self.led.sync() # registers the error
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|
self.core.break_realtime()
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|
self.spi0.set_config_mu() # raises the error
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|
|
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|
|
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|
class SPITest(ExperimentCase):
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|
def test_collision(self):
|
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|
with self.assertRaises(RTIOCollision):
|
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|
self.execute(Collision)
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|
|
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|
def test_busy(self):
|
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|
with self.assertRaises(RTIOBusy):
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|
self.execute(Busy)
|
@ -109,7 +109,7 @@ class ExperimentCase(unittest.TestCase):
|
|||||||
# skip if ddb does not match requirements
|
# skip if ddb does not match requirements
|
||||||
raise unittest.SkipTest(*e.args)
|
raise unittest.SkipTest(*e.args)
|
||||||
|
|
||||||
def execute(self, cls, *args, **kwargs):
|
def execute(self, cls, **kwargs):
|
||||||
expid = {
|
expid = {
|
||||||
"file": sys.modules[cls.__module__].__file__,
|
"file": sys.modules[cls.__module__].__file__,
|
||||||
"class_name": cls.__name__,
|
"class_name": cls.__name__,
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@ -124,3 +124,8 @@ class ExperimentCase(unittest.TestCase):
|
|||||||
except CompileError as error:
|
except CompileError as error:
|
||||||
# Reduce amount of text on terminal.
|
# Reduce amount of text on terminal.
|
||||||
raise error from None
|
raise error from None
|
||||||
|
except Exception as exn:
|
||||||
|
if hasattr(exn, "artiq_core_exception"):
|
||||||
|
exn.args = "{}\n{}".format(exn.args[0],
|
||||||
|
exn.artiq_core_exception),
|
||||||
|
raise exn
|
||||||
|
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