From f4c6d6eb69a6969fd687106cf6dfe752c5e86285 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 28 Nov 2016 15:18:54 +0800 Subject: [PATCH] kc705_drtio_master: fix number of fine RTIO timestamp bits --- artiq/gateware/targets/kc705_drtio_master.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/artiq/gateware/targets/kc705_drtio_master.py b/artiq/gateware/targets/kc705_drtio_master.py index f1de131cb..2d32bd0e3 100755 --- a/artiq/gateware/targets/kc705_drtio_master.py +++ b/artiq/gateware/targets/kc705_drtio_master.py @@ -54,7 +54,7 @@ class Master(MiniSoC, AMPSoC): phy = ttl_simple.Inout(platform.request(sma)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) - self.submodules.rtio_core = rtio.Core(rtio_channels, 4) + self.submodules.rtio_core = rtio.Core(rtio_channels, 2) self.submodules.cridec = rtio.CRIDecoder([self.drtio.cri, self.rtio_core.cri]) self.submodules.rtio = rtio.KernelInitiator(self.cridec.master)