mirror of https://github.com/m-labs/artiq
phaser: remove non-functional SPI examples
Those will be reimplemented after we have converter SPI access, but this will not be part of the 3.0 release.pull/668/merge
parent
70a3b66c76
commit
f3c7a7de3b
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@ -1,60 +0,0 @@
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# TODO: move to firmware
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from artiq.coredevice.ad9154_reg import *
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from artiq.experiment import *
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class Test(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.setattr_device("ad9154")
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@kernel
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def run(self):
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for i in range(1, 4): # prbs7, prbs15, prbs31
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self.prbs(i, 10)
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@kernel
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def busywait_us(self, t):
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t = self.core.get_rtio_counter_mu() + self.core.seconds_to_mu(t*us)
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while self.core.get_rtio_counter_mu() < t:
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pass
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def p(self, f, *a):
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print(f.format(*a))
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@kernel
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def prbs(self, p, t):
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self.p("---\nprbs sequence {}, threshold {}:", p, t)
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self.ad9154.jesd_prbs(p)
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self.ad9154.dac_write(AD9154_PHY_PRBS_TEST_CTRL,
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AD9154_PHY_PRBS_PAT_SEL_SET(p))
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self.ad9154.dac_write(AD9154_PHY_PRBS_TEST_EN, 0xff)
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self.ad9154.dac_write(AD9154_PHY_PRBS_TEST_CTRL,
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AD9154_PHY_PRBS_PAT_SEL_SET(p) | AD9154_PHY_TEST_RESET_SET(1))
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self.ad9154.dac_write(AD9154_PHY_PRBS_TEST_CTRL,
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AD9154_PHY_PRBS_PAT_SEL_SET(p))
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self.ad9154.dac_write(AD9154_PHY_PRBS_TEST_THRESHOLD_LOBITS, t)
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self.ad9154.dac_write(AD9154_PHY_PRBS_TEST_THRESHOLD_MIDBITS, t >> 8)
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self.ad9154.dac_write(AD9154_PHY_PRBS_TEST_THRESHOLD_MIDBITS, t >> 16)
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self.ad9154.dac_write(AD9154_PHY_PRBS_TEST_CTRL, AD9154_PHY_PRBS_PAT_SEL_SET(p))
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self.ad9154.dac_write(AD9154_PHY_PRBS_TEST_CTRL,
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AD9154_PHY_PRBS_PAT_SEL_SET(p) | AD9154_PHY_TEST_START_SET(1))
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self.busywait_us(1000000)
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self.ad9154.dac_write(AD9154_PHY_PRBS_TEST_CTRL, AD9154_PHY_PRBS_PAT_SEL_SET(p))
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self.p("prbs status: {:#04x}", self.ad9154.dac_read(AD9154_PHY_PRBS_TEST_STATUS))
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for i in range(8):
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self.ad9154.dac_write(AD9154_PHY_PRBS_TEST_CTRL, AD9154_PHY_SRC_ERR_CNT_SET(i))
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self.p("prbs errors[{}]: {:#08x}", i,
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self.ad9154.dac_read(AD9154_PHY_PRBS_TEST_ERRCNT_LOBITS) |
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(self.ad9154.dac_read(AD9154_PHY_PRBS_TEST_ERRCNT_MIDBITS) << 8) |
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(self.ad9154.dac_read(AD9154_PHY_PRBS_TEST_ERRCNT_HIBITS) << 16))
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self.ad9154.jesd_prbs(0)
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@ -1,140 +0,0 @@
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# TODO: move to firmware
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from artiq.coredevice.ad9154_reg import *
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from artiq.experiment import *
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class Test(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.setattr_device("ad9154")
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@kernel
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def run(self):
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self.print_status()
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self.print_temp()
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def p(self, f, *a):
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print(f % a)
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@kernel
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def print_temp(self):
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self.ad9154.dac_write(AD9154_DIE_TEMP_CTRL0, AD9154_AUXADC_RESERVED_SET(0x10) |
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AD9154_AUXADC_ENABLE_SET(1))
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self.ad9154.dac_write(AD9154_DIE_TEMP_UPDATE, 1)
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self.p("temp_code %d", self.ad9154.dac_read(AD9154_DIE_TEMP0) |
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(self.ad9154.dac_read(AD9154_DIE_TEMP1) << 8))
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self.ad9154.dac_write(AD9154_DIE_TEMP_CTRL0, AD9154_AUXADC_RESERVED_SET(0x10) |
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AD9154_AUXADC_ENABLE_SET(0))
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@kernel
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def print_status(self):
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x = self.ad9154.dac_read(AD9154_IRQ_STATUS0)
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self.p("LANEFIFOERR: %d, SERPLLLOCK: %d, SERPLLLOST: %d, "
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"DACPLLLOCK: %d, DACPLLLOST: %d",
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AD9154_LANEFIFOERR_GET(x), AD9154_SERPLLLOCK_GET(x),
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AD9154_SERPLLLOST_GET(x), AD9154_DACPLLLOCK_GET(x),
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AD9154_DACPLLLOST_GET(x))
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x = self.ad9154.dac_read(AD9154_IRQ_STATUS1)
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self.p("PRBS0: %d, PRBS1: %d, PRBS2: %d, PRBS3: %d",
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AD9154_PRBS0_GET(x), AD9154_PRBS1_GET(x),
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AD9154_PRBS2_GET(x), AD9154_PRBS3_GET(x))
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x = self.ad9154.dac_read(AD9154_IRQ_STATUS2)
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self.p("SYNC_TRIP0: %d, SYNC_WLIM0: %d, SYNC_ROTATE0: %d, "
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"SYNC_LOCK0: %d, NCO_ALIGN0: %d, BLNKDONE0: %d, "
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"PDPERR0: %d",
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AD9154_SYNC_TRIP0_GET(x), AD9154_SYNC_WLIM0_GET(x),
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AD9154_SYNC_ROTATE0_GET(x), AD9154_SYNC_LOCK0_GET(x),
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AD9154_NCO_ALIGN0_GET(x), AD9154_BLNKDONE0_GET(x),
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AD9154_PDPERR0_GET(x))
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x = self.ad9154.dac_read(AD9154_IRQ_STATUS3)
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self.p("SYNC_TRIP1: %d, SYNC_WLIM1: %d, SYNC_ROTATE1: %d, "
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"SYNC_LOCK1: %d, NCO_ALIGN1: %d, BLNKDONE1: %d, "
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"PDPERR1: %d",
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AD9154_SYNC_TRIP1_GET(x), AD9154_SYNC_WLIM1_GET(x),
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AD9154_SYNC_ROTATE1_GET(x), AD9154_SYNC_LOCK1_GET(x),
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AD9154_NCO_ALIGN1_GET(x), AD9154_BLNKDONE1_GET(x),
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AD9154_PDPERR1_GET(x))
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x = self.ad9154.dac_read(AD9154_JESD_CHECKS)
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self.p("ERR_INTSUPP: %d, ERR_SUBCLASS: %d, ERR_KUNSUPP: %d, "
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"ERR_JESDBAD: %d, ERR_WINLIMIT: %d, ERR_DLYOVER: %d",
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AD9154_ERR_INTSUPP_GET(x), AD9154_ERR_SUBCLASS_GET(x),
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AD9154_ERR_KUNSUPP_GET(x), AD9154_ERR_JESDBAD_GET(x),
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AD9154_ERR_WINLIMIT_GET(x), AD9154_ERR_DLYOVER_GET(x))
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x = self.ad9154.dac_read(AD9154_DACPLLSTATUS)
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self.p("DACPLL_LOCK: %d, VCO_CAL_PROGRESS: %d, CP_CAL_VALID: %d, "
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"CP_OVERRANGE_L: %d, CP_OVERRANGE_H: %d",
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AD9154_DACPLL_LOCK_GET(x), AD9154_VCO_CAL_PROGRESS_GET(x),
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AD9154_CP_CAL_VALID_GET(x), AD9154_CP_OVERRANGE_L_GET(x),
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AD9154_CP_OVERRANGE_H_GET(x))
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x = self.ad9154.dac_read(AD9154_PLL_STATUS)
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self.p("PLL_LOCK_RB: %d, CURRENTS_READY_RB: %d, "
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"VCO_CAL_IN_PROGRESS_RB: %d, PLL_CAL_VALID_RB: %d, "
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"PLL_OVERRANGE_L_RB: %d, PLL_OVERRANGE_H_RB: %d",
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AD9154_SERDES_PLL_LOCK_RB_GET(x),
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AD9154_SERDES_CURRENTS_READY_RB_GET(x),
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AD9154_SERDES_VCO_CAL_IN_PROGRESS_RB_GET(x),
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AD9154_SERDES_PLL_CAL_VALID_RB_GET(x),
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AD9154_SERDES_PLL_OVERRANGE_L_RB_GET(x),
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AD9154_SERDES_PLL_OVERRANGE_H_RB_GET(x))
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self.p("CODEGRPSYNC: 0x%02x", self.ad9154.dac_read(AD9154_CODEGRPSYNCFLG))
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self.p("FRAMESYNC: 0x%02x", self.ad9154.dac_read(AD9154_FRAMESYNCFLG))
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self.p("GOODCHECKSUM: 0x%02x", self.ad9154.dac_read(AD9154_GOODCHKSUMFLG))
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self.p("INITIALLANESYNC: 0x%02x", self.ad9154.dac_read(AD9154_INITLANESYNCFLG))
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x = self.ad9154.dac_read(AD9154_SYNC_CURRERR_H)
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self.p("SYNC_CURRERR: 0x%04x", self.ad9154.dac_read(AD9154_SYNC_CURRERR_L) |
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(AD9154_CURRERROR_H_GET(x) << 8))
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self.p("SYNC_CURROVER: %d, SYNC_CURRUNDER: %d",
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AD9154_CURROVER_GET(x), AD9154_CURRUNDER_GET(x))
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x = self.ad9154.dac_read(AD9154_SYNC_LASTERR_H)
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self.p("SYNC_LASTERR: 0x%04x", self.ad9154.dac_read(AD9154_SYNC_LASTERR_L) |
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(AD9154_LASTERROR_H_GET(x) << 8))
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self.p("SYNC_LASTOVER: %d, SYNC_LASTUNDER: %d",
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AD9154_LASTOVER_GET(x), AD9154_LASTUNDER_GET(x))
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x = self.ad9154.dac_read(AD9154_SYNC_STATUS)
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self.p("SYNC_TRIP: %d, SYNC_WLIM: %d, SYNC_ROTATE: %d, "
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"SYNC_LOCK: %d, SYNC_BUSY: %d",
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AD9154_SYNC_TRIP_GET(x), AD9154_SYNC_WLIM_GET(x),
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AD9154_SYNC_ROTATE_GET(x), AD9154_SYNC_LOCK_GET(x),
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AD9154_SYNC_BUSY_GET(x))
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self.p("LANE_FIFO_FULL: 0x%02x", self.ad9154.dac_read(AD9154_FIFO_STATUS_REG_0))
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self.p("LANE_FIFO_EMPTY: 0x%02x", self.ad9154.dac_read(AD9154_FIFO_STATUS_REG_1))
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self.p("DID_REG: 0x%02x", self.ad9154.dac_read(AD9154_DID_REG))
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self.p("BID_REG: 0x%02x", self.ad9154.dac_read(AD9154_BID_REG))
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self.p("SCR_L_REG: 0x%02x", self.ad9154.dac_read(AD9154_SCR_L_REG))
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self.p("F_REG: 0x%02x", self.ad9154.dac_read(AD9154_F_REG))
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self.p("K_REG: 0x%02x", self.ad9154.dac_read(AD9154_K_REG))
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self.p("M_REG: 0x%02x", self.ad9154.dac_read(AD9154_M_REG))
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self.p("CS_N_REG: 0x%02x", self.ad9154.dac_read(AD9154_CS_N_REG))
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self.p("NP_REG: 0x%02x", self.ad9154.dac_read(AD9154_NP_REG))
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self.p("S_REG: 0x%02x", self.ad9154.dac_read(AD9154_S_REG))
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self.p("HD_CF_REG: 0x%02x", self.ad9154.dac_read(AD9154_HD_CF_REG))
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self.p("RES1_REG: 0x%02x", self.ad9154.dac_read(AD9154_RES1_REG))
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self.p("RES2_REG: 0x%02x", self.ad9154.dac_read(AD9154_RES2_REG))
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self.p("LIDx_REG: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x",
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self.ad9154.dac_read(AD9154_LID0_REG), self.ad9154.dac_read(AD9154_LID1_REG),
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self.ad9154.dac_read(AD9154_LID2_REG), self.ad9154.dac_read(AD9154_LID3_REG),
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self.ad9154.dac_read(AD9154_LID4_REG), self.ad9154.dac_read(AD9154_LID5_REG),
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self.ad9154.dac_read(AD9154_LID6_REG), self.ad9154.dac_read(AD9154_LID7_REG))
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self.p("CHECKSUMx_REG: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x",
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self.ad9154.dac_read(AD9154_CHECKSUM0_REG), self.ad9154.dac_read(AD9154_CHECKSUM1_REG),
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self.ad9154.dac_read(AD9154_CHECKSUM2_REG), self.ad9154.dac_read(AD9154_CHECKSUM3_REG),
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self.ad9154.dac_read(AD9154_CHECKSUM4_REG), self.ad9154.dac_read(AD9154_CHECKSUM5_REG),
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self.ad9154.dac_read(AD9154_CHECKSUM6_REG), self.ad9154.dac_read(AD9154_CHECKSUM7_REG))
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self.p("COMPSUMx_REG: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x",
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self.ad9154.dac_read(AD9154_COMPSUM0_REG), self.ad9154.dac_read(AD9154_COMPSUM1_REG),
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self.ad9154.dac_read(AD9154_COMPSUM2_REG), self.ad9154.dac_read(AD9154_COMPSUM3_REG),
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self.ad9154.dac_read(AD9154_COMPSUM4_REG), self.ad9154.dac_read(AD9154_COMPSUM5_REG),
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self.ad9154.dac_read(AD9154_COMPSUM6_REG), self.ad9154.dac_read(AD9154_COMPSUM7_REG))
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self.p("BADDISPARITY: 0x%02x", self.ad9154.dac_read(AD9154_BADDISPARITY))
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self.p("NITDISPARITY: 0x%02x", self.ad9154.dac_read(AD9154_NIT_W))
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self.p("UNEXPECTEDCONTROL: 0x%02x", self.ad9154.dac_read(AD9154_UNEXPECTEDCONTROL_W))
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self.p("DYN_LINK_LATENCY_0: 0x%02x",
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self.ad9154.dac_read(AD9154_DYN_LINK_LATENCY_0))
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self.p("DYN_LINK_LATENCY_1: 0x%02x",
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self.ad9154.dac_read(AD9154_DYN_LINK_LATENCY_1))
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@ -1,52 +0,0 @@
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# TODO: move to firmware
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from jesd204b.transport import seed_to_data
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from artiq.coredevice.ad9154_reg import *
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from artiq.experiment import *
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class Test(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.setattr_device("ad9154")
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def run(self):
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self.ad9154.jesd_stpl(1)
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# short transport layer test
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for i in range(4):
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data = seed_to_data(i << 8, True)
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fail = self.stpl(i, data)
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print("channel", i, "FAIL" if fail else "PASS")
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self.ad9154.jesd_stpl(0)
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@kernel
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def stpl(self, i, data):
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# select dac
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self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
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AD9154_SHORT_TPL_TEST_EN_SET(0) |
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AD9154_SHORT_TPL_TEST_RESET_SET(0) |
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AD9154_SHORT_TPL_DAC_SEL_SET(i) |
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AD9154_SHORT_TPL_SP_SEL_SET(0))
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# set expected value
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self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_1, data & 0xff)
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self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_2, (data & 0xff00) >> 8)
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# enable stpl
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self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
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AD9154_SHORT_TPL_TEST_EN_SET(1) |
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AD9154_SHORT_TPL_TEST_RESET_SET(0) |
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AD9154_SHORT_TPL_DAC_SEL_SET(i) |
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AD9154_SHORT_TPL_SP_SEL_SET(0))
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# reset stpl
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self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
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AD9154_SHORT_TPL_TEST_EN_SET(1) |
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AD9154_SHORT_TPL_TEST_RESET_SET(1) |
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AD9154_SHORT_TPL_DAC_SEL_SET(i) |
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AD9154_SHORT_TPL_SP_SEL_SET(0))
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# release reset stpl
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self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
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AD9154_SHORT_TPL_TEST_EN_SET(1) |
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AD9154_SHORT_TPL_TEST_RESET_SET(0) |
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AD9154_SHORT_TPL_DAC_SEL_SET(i) |
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AD9154_SHORT_TPL_SP_SEL_SET(0))
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return self.ad9154.dac_read(AD9154_SHORT_TPL_TEST_3)
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