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Updated qc2 pinouts for SPI and 2x DDS bus, update docs

This commit is contained in:
dhslichter 2016-04-12 11:40:58 -06:00 committed by Sebastien Bourdeauducq
parent 5788c02a10
commit f395a630e0
3 changed files with 85 additions and 27 deletions
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33
artiq/gateware/nist_qc2.py
View File

@ -8,9 +8,8 @@ __all__ = ["fmc_adapter_io"]
ttl_pins = [
"LA00_CC_P", "LA02_P", "LA00_CC_N", "LA02_N", "LA01_CC_P", "LA01_CC_N", "LA06_P", "LA06_N",
"LA05_P", "LA05_N", "LA10_P", "LA09_P", "LA10_N", "LA09_N", "LA13_P", "LA14_P", "LA13_N",
"LA14_N", "LA17_CC_P", "LA17_CC_N", "LA18_CC_P", "LA18_CC_N", "LA23_P", "LA23_N", "LA27_P",
"LA26_P", "LA27_N", "LA26_N"
"LA05_P", "LA05_N", "LA10_P", "LA09_P", "LA10_N", "LA09_N", "LA13_P", "LA14_P",
"LA27_P", "LA26_P", "LA27_N", "LA26_N"
]
@ -18,7 +17,8 @@ def get_fmc_adapter_io():
ttl = itertools.count()
dds = itertools.count()
i2c_fmc = itertools.count()
clk_m2c = itertools.count()
spi = itertools.count()
clkout = itertools.count()
r = []
for connector in "LPC", "HPC":
@ -50,15 +50,24 @@ def get_fmc_adapter_io():
Subsignal("sda", FPins("FMC:IIC_SDA")),
IOStandard("LVCMOS25")),
("clk_m2c", next(clk_m2c),
Subsignal("p", FPins("FMC:CLK0_M2C_P")),
Subsignal("n", FPins("FMC:CLK0_M2C_N")),
IOStandard("LVDS")),
("clkout", next(clkout), FPins("FMC:CLK1_M2C_P"),
IOStandard("LVTTL")),
("spi", next(spi),
Subsignal("clk", Pins("FMC:LA13_N")),
Subsignal("mosi", Pins("FMC:LA14_N")),
Subsignal("miso", Pins("FMC:LA17_CC_P")),
Subsignal("cs_n", Pins("FMC:LA17_CC_N")),
IOStandard("LVTTL")),
("spi", next(spi),
Subsignal("clk", Pins("FMC:LA18_CC_P")),
Subsignal("mosi", Pins("FMC:LA18_CC_N")),
Subsignal("miso", Pins("FMC:LA23_P")),
Subsignal("cs_n", Pins("FMC:LA23_N")),
IOStandard("LVTTL")),
("clk_m2c", next(clk_m2c),
Subsignal("p", FPins("FMC:CLK1_M2C_P")),
Subsignal("n", FPins("FMC:CLK1_M2C_N")),
IOStandard("LVDS")),
]
return r

38
artiq/gateware/targets/kc705.py
View File

@ -300,7 +300,7 @@ class NIST_CLOCK(_NIST_Ions):
class NIST_QC2(_NIST_Ions):
"""
NIST QC2 hardware, as used in Quantum I and Quantum II, with new backplane
and 24 DDS channels.
and 24 DDS channels. Two backplanes are used.
"""
def __init__(self, cpu_type="or1k", **kwargs):
_NIST_Ions.__init__(self, cpu_type, **kwargs)
@ -310,36 +310,56 @@ class NIST_QC2(_NIST_Ions):
rtio_channels = []
clock_generators = []
for backplane_offset in 0, 28:
# TTL0-23 are In+Out capable
for i in range(24):
for backplane_offset in 0, 20:
# TTL0-15, 20-35 are In+Out capable
for i in range(16):
phy = ttl_serdes_7series.Inout_8X(
platform.request("ttl", backplane_offset+i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
# TTL24-26 are output only
for i in range(24, 27):
# TTL16-19, 36-39 are output only
for i in range(16, 20):
phy = ttl_serdes_7series.Output_8X(
platform.request("ttl", backplane_offset+i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
# TTL27 is for the clock generator
# CLK0, CLK1 are for the clock generators, on backplane SMP connectors
for backplane_offset in range(2):
phy = ttl_simple.ClockGen(
platform.request("ttl", backplane_offset+27))
platform.request("clkout", backplane_offset))
self.submodules += phy
clock_generators.append(rtio.Channel.from_phy(phy))
clock_generators.append(rtio.Channel.from_phy(phy))
phy = ttl_serdes_7series.Inout_8X(platform.request("user_sma_gpio_n"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
phy = ttl_simple.Output(platform.request("user_led", 2))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
ams101_dac = self.platform.request("ams101_dac", 0)
phy = ttl_simple.Output(ams101_dac.ldac)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
# add clock generators after RTIO_REGULAR_TTL_COUNT
rtio_channels += clock_generators
phy = spi.SPIMaster(ams101_dac)
self.submodules += phy
self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.Channel.from_phy(
phy, ofifo_depth=4, ififo_depth=4))
for i in range(4):
phy = spi.SPIMaster(self.platform.request("spi", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(
phy, ofifo_depth=128, ififo_depth=128))
self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels)
self.config["RTIO_DDS_COUNT"] = 2
self.config["DDS_CHANNELS_PER_BUS"] = 12

41
doc/manual/core_device.rst
View File

@ -101,7 +101,40 @@ NIST QC2
With the QC2 hardware, the TTL lines are mapped as follows:
TODO
+--------------------+-----------------------+--------------+
| RTIO channel | TTL line | Capability |
+====================+=======================+==============+
| 0-15, 20-35 | TTL0-15, TTL20-35 | Input+Output |
+--------------------+-----------------------+--------------+
| 16-19, 36-39 | TTL16-19, TTL36-39 | Output |
+--------------------+-----------------------+--------------+
| 40 | SMA_GPIO_N | Input+Output |
+--------------------+-----------------------+--------------+
| 41 | LED | Output |
+--------------------+-----------------------+--------------+
| 42 | AMS101_LDAC_B | Output |
+--------------------+-----------------------+--------------+
| 43, 44 | CLK0, CLK1 | Clock |
+--------------------+-----------------------+--------------+
The board has RTIO SPI buses mapped as follows:
+--------------+-------------+-------------+-----------+------------+
| RTIO channel | CS_N | MOSI | MISO | CLK |
+==============+=============+=============+===========+============+
| 45 | AMS101_CS_N | AMS101_MOSI | | AMS101_CLK |
+--------------+-------------+-------------+-----------+------------+
| 46 | SPI0_CS_N | SPI0_MOSI | SPI0_MISO | SPI0_CLK |
+--------------+-------------+-------------+-----------+------------+
| 47 | SPI1_CS_N | SPI1_MOSI | SPI1_MISO | SPI1_CLK |
+--------------+-------------+-------------+-----------+------------+
| 48 | SPI2_CS_N | SPI2_MOSI | SPI2_MISO | SPI2_CLK |
+--------------+-------------+-------------+-----------+------------+
| 49 | SPI3_CS_N | SPI3_MOSI | SPI3_MISO | SPI3_CLK |
+--------------+-------------+-------------+-----------+------------+
There are two DDS buses on channels 50 (LPC, DDS0-DDS11) and 51 (HPC, DDS12-DDS23).
The QC2 hardware uses TCA6424A I2C I/O expanders to define the directions of its TTL buffers. There is one such expander per FMC card, and they are selected using the PCA9548 on the KC705.
@ -109,11 +142,7 @@ To avoid I/O contention, the startup kernel should first program the TCA6424A ex
See :mod:`artiq.coredevice.i2c` for more details.
There are no SPI channels.
The QC2 hardware has two DDS buses, on channels TODO for LPC and TODO for HPC.
For the safe operation of the DDS buses, the FMC voltage of the KC705 should be changed to 3.3V. Plug the TI USB PMBus adapter to the PMBus connector in the corner of the KC705 and use the Fusion Digital Power Designer software (requires Windows). Write to chip number U55 (address 52), channel 4, which is VADJ, to make it 3.3V instead of 2.5V.
For safe operation of the DDS buses (to prevent damage to the IO banks of the FPGA), the FMC VADJ rail of the KC705 should be changed to 3.3V. Plug the Texas Instruments USB-TO-GPIO PMBus adapter into the PMBus connector in the corner of the KC705 and use the Fusion Digital Power Designer software to configure (requires Windows). Write to chip number U55 (address 52), channel 4, which is the VADJ rail, to make it 3.3V instead of 2.5V. Power cycle the KC705 board to check that the startup voltage on the VADJ rail is now 3.3V.
Pipistrello
-----------