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Revert "ad9154: use continuous sync mode" 

The HMC7043 is not really glitchless.

This reverts commit bd968211de.
This commit is contained in:
Sebastien Bourdeauducq 2018-08-06 16:59:53 +08:00
parent 65f198bdee
commit f32f0126e2
2 changed files with 33 additions and 18 deletions
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29
artiq/firmware/libboard_artiq/ad9154.rs
View File

@ -371,9 +371,27 @@ fn dac_setup(dacno: u8, linerate: u64) -> Result<(), &'static str> {
write(ad9154_reg::LMFC_VAR_1, 0x0a); write(ad9154_reg::LMFC_VAR_1, 0x0a);
write(ad9154_reg::SYNC_ERRWINDOW, 0); // +- 1/2 DAC clock write(ad9154_reg::SYNC_ERRWINDOW, 0); // +- 1/2 DAC clock
write(ad9154_reg::SYNC_CONTROL, write(ad9154_reg::SYNC_CONTROL,
0x2*ad9154_reg::SYNCMODE | 1*ad9154_reg::SYNCENABLE | 0x9*ad9154_reg::SYNCMODE | 0*ad9154_reg::SYNCENABLE |
0*ad9154_reg::SYNCARM | 1*ad9154_reg::SYNCCLRSTKY |
1*ad9154_reg::SYNCCLRLAST); 1*ad9154_reg::SYNCCLRLAST);
write(ad9154_reg::SYNC_CONTROL,
0x9*ad9154_reg::SYNCMODE | 1*ad9154_reg::SYNCENABLE |
0*ad9154_reg::SYNCARM | 1*ad9154_reg::SYNCCLRSTKY |
1*ad9154_reg::SYNCCLRLAST);
write(ad9154_reg::SYNC_CONTROL,
0x9*ad9154_reg::SYNCMODE | 1*ad9154_reg::SYNCENABLE |
1*ad9154_reg::SYNCARM | 0*ad9154_reg::SYNCCLRSTKY |
0*ad9154_reg::SYNCCLRLAST);
clock::spin_us(1000); // ensure at least one sysref edge
if read(ad9154_reg::SYNC_CONTROL) & ad9154_reg::SYNCARM != 0 {
return Err("no sysref edge");
}
if read(ad9154_reg::SYNC_STATUS) & ad9154_reg::SYNC_LOCK == 0 {
return Err("no sync lock");
}
if read(ad9154_reg::SYNC_STATUS) & ad9154_reg::SYNC_WLIM != 0 {
return Err("sysref phase error");
}
write(ad9154_reg::XBAR_LN_0_1, write(ad9154_reg::XBAR_LN_0_1,
0*ad9154_reg::LOGICAL_LANE0_SRC | 1*ad9154_reg::LOGICAL_LANE1_SRC); 0*ad9154_reg::LOGICAL_LANE0_SRC | 1*ad9154_reg::LOGICAL_LANE1_SRC);
write(ad9154_reg::XBAR_LN_2_3, write(ad9154_reg::XBAR_LN_2_3,
@ -671,12 +689,9 @@ fn dac_cfg_retry(dacno: u8) -> Result<(), &'static str> {
pub fn dac_get_sync_error(dacno: u8) -> u16 { pub fn dac_get_sync_error(dacno: u8) -> u16 {
spi_setup(dacno); spi_setup(dacno);
let sync_error = ((read(ad9154_reg::SYNC_LASTERR_L) as u16) | let sync_error = ((read(ad9154_reg::SYNC_CURRERR_L) as u16) |
((read(ad9154_reg::SYNC_LASTERR_H) as u16) << 8)) ((read(ad9154_reg::SYNC_CURRERR_H) as u16) << 8))
& 0x1ff; & 0x1ff;
write(ad9154_reg::SYNC_CONTROL,
0x2*ad9154_reg::SYNCMODE | 1*ad9154_reg::SYNCENABLE |
1*ad9154_reg::SYNCCLRLAST);
sync_error sync_error
} }

22
artiq/firmware/libboard_artiq/jesd204sync.rs
View File

@ -148,13 +148,13 @@ fn sysref_cal_dac(dacno: u8) -> Result<u16, &'static str> {
hmc7043::sysref_offset_dac(dacno, d); hmc7043::sysref_offset_dac(dacno, d);
clock::spin_us(10000); clock::spin_us(10000);
ad9154::dac_get_sync_error(dacno); // clear SYNC_LASTERR let sync_error_last = ad9154::dac_get_sync_error(dacno);
loop { loop {
hmc7043::sysref_offset_dac(dacno, d); hmc7043::sysref_offset_dac(dacno, d);
clock::spin_us(10000); clock::spin_us(10000);
let sync_error = ad9154::dac_get_sync_error(dacno); let sync_error = ad9154::dac_get_sync_error(dacno);
if sync_error != 0 { if sync_error != sync_error_last {
dmin = d; dmin = d;
break; break;
} }
@ -165,16 +165,16 @@ fn sysref_cal_dac(dacno: u8) -> Result<u16, &'static str> {
} }
} }
d += 17; // get away from jitter d += 5; // get away from jitter
hmc7043::sysref_offset_dac(dacno, d); hmc7043::sysref_offset_dac(dacno, d);
clock::spin_us(10000); clock::spin_us(10000);
ad9154::dac_get_sync_error(dacno); // clear SYNC_LASTERR let sync_error_last = ad9154::dac_get_sync_error(dacno);
loop { loop {
hmc7043::sysref_offset_dac(dacno, d); hmc7043::sysref_offset_dac(dacno, d);
clock::spin_us(10000); clock::spin_us(10000);
let sync_error = ad9154::dac_get_sync_error(dacno); let sync_error = ad9154::dac_get_sync_error(dacno);
if sync_error != 0 { if sync_error != sync_error_last {
dmax = d; dmax = d;
break; break;
} }
@ -198,13 +198,13 @@ fn sysref_dac_align(dacno: u8, phase: u16) -> Result<(), &'static str> {
hmc7043::sysref_offset_dac(dacno, phase); hmc7043::sysref_offset_dac(dacno, phase);
clock::spin_us(10000); clock::spin_us(10000);
ad9154::dac_get_sync_error(dacno); // clear SYNC_LASTERR let sync_error_last = ad9154::dac_get_sync_error(dacno);
for d in 0..128 { for d in 0..128 {
hmc7043::sysref_offset_dac(dacno, phase - d); hmc7043::sysref_offset_dac(dacno, phase - d);
clock::spin_us(10000); clock::spin_us(10000);
let sync_error = ad9154::dac_get_sync_error(dacno); let sync_error = ad9154::dac_get_sync_error(dacno);
if sync_error != 0 { if sync_error != sync_error_last {
info!(" sync error-: {}", sync_error); info!(" sync error-: {} -> {}", sync_error_last, sync_error);
margin_minus = Some(d); margin_minus = Some(d);
break; break;
} }
@ -212,13 +212,13 @@ fn sysref_dac_align(dacno: u8, phase: u16) -> Result<(), &'static str> {
hmc7043::sysref_offset_dac(dacno, phase); hmc7043::sysref_offset_dac(dacno, phase);
clock::spin_us(10000); clock::spin_us(10000);
ad9154::dac_get_sync_error(dacno); // clear SYNC_LASTERR let sync_error_last = ad9154::dac_get_sync_error(dacno);
for d in 0..128 { for d in 0..128 {
hmc7043::sysref_offset_dac(dacno, phase + d); hmc7043::sysref_offset_dac(dacno, phase + d);
clock::spin_us(10000); clock::spin_us(10000);
let sync_error = ad9154::dac_get_sync_error(dacno); let sync_error = ad9154::dac_get_sync_error(dacno);
if sync_error != 0 { if sync_error != sync_error_last {
info!(" sync error+: {}", sync_error); info!(" sync error+: {} -> {}", sync_error_last, sync_error);
margin_plus = Some(d); margin_plus = Some(d);
break; break;
} }