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nist_clock: disable spi1/2

This commit is contained in:
Robert Jördens 2016-03-01 01:52:46 +01:00
parent 7d7a710a56
commit f2ec8692c0
2 changed files with 2 additions and 14 deletions
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2
artiq/gateware/targets/kc705.py
View File

@ -262,7 +262,7 @@ class NIST_CLOCK(_NIST_Ions):
rtio_channels.append(rtio.Channel.from_phy(
phy, ofifo_depth=4, ififo_depth=4))
for i in range(3):
for i in range(1): # spi1 and spi2 collide in pinout with ttl
phy = spi.SPIMaster(self.platform.request("spi", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(

14
examples/master/device_db.pyon
View File

@ -100,24 +100,12 @@
"class": "SPIMaster",
"arguments": {"channel": 22}
},
"spi1": {
"type": "local",
"module": "artiq.coredevice.spi",
"class": "SPIMaster",
"arguments": {"channel": 23}
},
"spi2": {
"type": "local",
"module": "artiq.coredevice.spi",
"class": "SPIMaster",
"arguments": {"channel": 24}
},
"ttl_clock_la32_p": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLClockGen",
"arguments": {"channel": 25}
"arguments": {"channel": 23}
},
"dds_bus": {