rtio/dma: remove dead/broken code

2020-07-12 10:13:18 +08:00 · 2020-07-12 10:13:18 +08:00 · f2e0d27334
parent 901be75ba4
commit f2e0d27334
1 changed files with 1 additions and 3 deletions
--- a/artiq/gateware/rtio/dma.py
+++ b/artiq/gateware/rtio/dma.py
@ -12,9 +12,7 @@ def _reverse_bytes(s, g):


 class WishboneReader(Module):
-    def __init__(self, bus=None):
-        if bus is None:
-            bus = wishbone.Interface
+    def __init__(self):
        self.bus = bus

        aw = len(bus.adr)