mirror of https://github.com/m-labs/artiq
phaser: iotest early, check_alarms
parent
b15e388b5f
commit
f0959fb871
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@ -169,44 +169,6 @@ class Phaser:
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t = self.get_dac_temperature()
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if t < 10 or t > 90:
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raise ValueError("DAC temperature out of bounds")
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delay(.1*ms)
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delay(.5*ms) # slack
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self.dac_write(0x00, 0x019c) # I=2, fifo, clkdiv_sync, qmc off
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self.dac_write(0x01, 0x040e) # fifo alarms, parity
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self.dac_write(0x02, 0x70a2) # clk alarms, sif4, nco off, mix, mix_gain, 2s
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self.dac_write(0x03, 0x4000) # coarse dac 20.6 mA
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self.dac_write(0x07, 0x40c1) # alarm mask
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self.dac_write(0x09, 0x4000) # fifo_offset
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self.dac_write(0x0d, 0x0000) # fmix, no cmix
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self.dac_write(0x14, 0x5431) # fine nco ab
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self.dac_write(0x15, 0x0323) # coarse nco ab
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self.dac_write(0x16, 0x5431) # fine nco cd
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self.dac_write(0x17, 0x0323) # coarse nco cd
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self.dac_write(0x18, 0x2c60) # P=4, pll run, single cp, pll_ndivsync
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self.dac_write(0x19, 0x8814) # M=16 N=2
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self.dac_write(0x1a, 0xfc00) # pll_vco=63, 4 GHz
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delay(.2*ms) # slack
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self.dac_write(0x1b, 0x0800) # int ref, fuse
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self.dac_write(0x1e, 0x9999) # qmc sync from sif and reg
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self.dac_write(0x1f, 0x9982) # mix sync, nco sync, istr is istr, sif_sync
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self.dac_write(0x20, 0x2400) # fifo sync ISTR-OSTR
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self.dac_write(0x22, 0x1be4) # reverse dacs for spectral inversion and layout
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self.dac_write(0x24, 0x0000) # clk and data delays
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self.clear_dac_alarms()
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delay(1*ms) # lock pll
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lvolt = self.dac_read(0x18) & 7
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delay(.1*ms)
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if lvolt < 2 or lvolt > 5:
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raise ValueError("DAC PLL tuning voltage out of bounds")
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# self.dac_write(0x20, 0x0000) # stop fifo sync
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# alarm = self.get_sta() & 1
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# delay(.1*ms)
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alarm = self.get_dac_alarms()
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if alarm & ~0x0040: # ignore PLL alarms (see DS)
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print(alarm)
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raise ValueError("DAC alarm")
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delay(.5*ms)
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patterns = [
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@ -228,6 +190,35 @@ class Phaser:
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if errors:
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raise ValueError("iotest error")
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delay(.5*ms)
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delay(.5*ms) # slack
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self.dac_write(0x00, 0x019c) # I=2, fifo, clkdiv_sync, qmc off
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self.dac_write(0x01, 0x040e) # fifo alarms, parity
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self.dac_write(0x02, 0x70a2) # clk alarms, sif4, nco off, mix, mix_gain, 2s
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self.dac_write(0x03, 0xa000) # coarse dac 20.6 mA
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self.dac_write(0x07, 0x40c1) # alarm mask
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self.dac_write(0x09, 0x4000) # fifo_offset
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self.dac_write(0x0d, 0x0000) # fmix, no cmix
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self.dac_write(0x14, 0x5431) # fine nco ab
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self.dac_write(0x15, 0x0323) # coarse nco ab
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self.dac_write(0x16, 0x5431) # fine nco cd
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self.dac_write(0x17, 0x0323) # coarse nco cd
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self.dac_write(0x18, 0x2c60) # P=4, pll run, single cp, pll_ndivsync
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self.dac_write(0x19, 0x8814) # M=16 N=2
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self.dac_write(0x1a, 0xfc00) # pll_vco=63, 4 GHz
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delay(.2*ms) # slack
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self.dac_write(0x1b, 0x0800) # int ref, fuse
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self.dac_write(0x1e, 0x9999) # qmc sync from sif and reg
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self.dac_write(0x1f, 0x9982) # mix sync, nco sync, istr is istr, sif_sync
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self.dac_write(0x20, 0x2400) # fifo sync ISTR-OSTR
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self.dac_write(0x22, 0x1be4) # reverse dacs for spectral inversion and layout
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self.dac_write(0x24, 0x0000) # clk and data delays
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delay(2*ms) # lock pll
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lvolt = self.dac_read(0x18) & 7
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delay(.1*ms)
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if lvolt < 2 or lvolt > 5:
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raise ValueError("DAC PLL tuning voltage out of bounds")
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self.clear_dac_alarms()
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hw_rev = self.read8(PHASER_ADDR_HW_REV)
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@ -236,8 +227,8 @@ class Phaser:
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for ch in range(2):
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# test attenuator write and readback
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self.channel[ch].set_att_mu(0x55)
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if self.channel[ch].get_att_mu() != 0x55:
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self.channel[ch].set_att_mu(0x5a)
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if self.channel[ch].get_att_mu() != 0x5a:
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raise ValueError("attenuator test failed")
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delay(.1*ms)
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self.channel[ch].set_att(31.5*dB)
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@ -250,6 +241,19 @@ class Phaser:
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raise ValueError("DAC test data readback failed")
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delay(.1*ms)
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# self.dac_write(0x20, 0x0000) # stop fifo sync
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# alarm = self.get_sta() & 1
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# delay(.1*ms)
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self.check_dac_alarms()
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@kernel
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def check_dac_alarms(self):
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alarm = self.get_dac_alarms()
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delay(.1*ms) # slack
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if alarm & ~0x0040: # ignore PLL alarms (see DS)
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print(alarm)
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raise ValueError("DAC alarm")
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@kernel
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def write8(self, addr, data):
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"""Write data to FPGA register.
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@ -506,11 +510,13 @@ class Phaser:
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# no need to go through the alarm register,
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# just read the error mask
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# self.clear_dac_alarms()
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# alarm = self.dac_read(0x05)
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# delay(.1*ms) # slack
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# if alarm & 0x0080: # alarm_from_iotest
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errors = self.dac_read(0x04)
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alarm = self.get_dac_alarms()
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delay(.1*ms) # slack
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if alarm & 0x0080: # alarm_from_iotest
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errors = self.dac_read(0x04)
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delay(.1*ms) # slack
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else:
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errors = 0
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self.dac_write(0x01, 0x0000) # clear config
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self.dac_write(0x04, 0x0000) # clear iotest_result
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return errors
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