2
0
mirror of https://github.com/m-labs/artiq.git synced 2024-12-26 03:38:25 +08:00

rtio: move CRI write comment to more appropriate location

This commit is contained in:
Sebastien Bourdeauducq 2018-03-29 23:55:00 +08:00
parent e83863a8da
commit f0771765c1
2 changed files with 5 additions and 5 deletions

View File

@ -6,6 +6,11 @@ from migen.genlib.record import *
from misoc.interconnect.csr import * from misoc.interconnect.csr import *
# CRI write happens in 3 cycles:
# 1. set timestamp and channel
# 2. set other payload elements and issue write command
# 3. check status
commands = { commands = {
"nop": 0, "nop": 0,

View File

@ -7,11 +7,6 @@ from artiq.gateware.rtio.sed import layouts
__all__ = ["LaneDistributor"] __all__ = ["LaneDistributor"]
# CRI write happens in 3 cycles:
# 1. set timestamp and channel
# 2. set other payload elements and issue write command
# 3. check status
class LaneDistributor(Module): class LaneDistributor(Module):
def __init__(self, lane_count, seqn_width, layout_payload, def __init__(self, lane_count, seqn_width, layout_payload,
compensation, glbl_fine_ts_width, compensation, glbl_fine_ts_width,