From f060d6e1b337b75f65590337063f1a7d00109a23 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 20 Feb 2018 18:50:35 +0800 Subject: [PATCH] drtio: increase A7 clock aligner check period --- artiq/gateware/drtio/transceiver/gtp_7series.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/artiq/gateware/drtio/transceiver/gtp_7series.py b/artiq/gateware/drtio/transceiver/gtp_7series.py index 397235e28..62d2728ef 100644 --- a/artiq/gateware/drtio/transceiver/gtp_7series.py +++ b/artiq/gateware/drtio/transceiver/gtp_7series.py @@ -689,7 +689,7 @@ class GTPSingle(Module): self.comb += decoders[i].input.eq(rxdata[10*i:10*(i+1)]) # clock alignment - clock_aligner = BruteforceClockAligner(0b0101111100, rtio_clk_freq, check_period=10e-3) + clock_aligner = BruteforceClockAligner(0b0101111100, rtio_clk_freq, check_period=12e-3) self.submodules += clock_aligner self.comb += [ clock_aligner.rxdata.eq(rxdata),