From f017d1771f1cbd8c589f69da30c4a398cc9f703e Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 25 Feb 2017 12:14:56 +0800 Subject: [PATCH] gateware: remove unused configs in targets (not needed with new moninj) --- artiq/gateware/targets/kc705_dds.py | 12 +----------- artiq/gateware/targets/kc705_drtio_master.py | 1 - artiq/gateware/targets/phaser.py | 2 -- artiq/gateware/targets/pipistrello.py | 3 --- 4 files changed, 1 insertion(+), 17 deletions(-) diff --git a/artiq/gateware/targets/kc705_dds.py b/artiq/gateware/targets/kc705_dds.py index 455ebdb8a..e1bd8445f 100755 --- a/artiq/gateware/targets/kc705_dds.py +++ b/artiq/gateware/targets/kc705_dds.py @@ -202,7 +202,6 @@ class NIST_CLOCK(_NIST_Ions): phy = ttl_simple.Output(ams101_dac.ldac) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) - self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels) phy = ttl_simple.ClockGen(platform.request("la32_p")) self.submodules += phy @@ -210,7 +209,6 @@ class NIST_CLOCK(_NIST_Ions): phy = spi.SPIMaster(ams101_dac) self.submodules += phy - self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.Channel.from_phy( phy, ofifo_depth=4, ififo_depth=4)) @@ -220,9 +218,6 @@ class NIST_CLOCK(_NIST_Ions): rtio_channels.append(rtio.Channel.from_phy( phy, ofifo_depth=128, ififo_depth=128)) - self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels) - self.config["RTIO_DDS_COUNT"] = 1 - self.config["DDS_CHANNELS_PER_BUS"] = 11 phy = dds.AD9914(platform.request("dds"), 11, onehot=True) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, @@ -278,14 +273,12 @@ class NIST_QC2(_NIST_Ions): phy = ttl_simple.Output(ams101_dac.ldac) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) - self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels) - # add clock generators after RTIO_REGULAR_TTL_COUNT + # add clock generators after TTLs rtio_channels += clock_generators phy = spi.SPIMaster(ams101_dac) self.submodules += phy - self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.Channel.from_phy( phy, ofifo_depth=4, ififo_depth=4)) @@ -295,9 +288,6 @@ class NIST_QC2(_NIST_Ions): rtio_channels.append(rtio.Channel.from_phy( phy, ofifo_depth=128, ififo_depth=128)) - self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels) - self.config["RTIO_DDS_COUNT"] = 2 - self.config["DDS_CHANNELS_PER_BUS"] = 12 for backplane_offset in range(2): phy = dds.AD9914( platform.request("dds", backplane_offset), 12, onehot=True) diff --git a/artiq/gateware/targets/kc705_drtio_master.py b/artiq/gateware/targets/kc705_drtio_master.py index 19951f40c..9e16ead4e 100755 --- a/artiq/gateware/targets/kc705_drtio_master.py +++ b/artiq/gateware/targets/kc705_drtio_master.py @@ -100,7 +100,6 @@ class Master(MiniSoC, AMPSoC): self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) - self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.csr_devices.append("rtio_moninj") diff --git a/artiq/gateware/targets/phaser.py b/artiq/gateware/targets/phaser.py index b2b10b0cd..62a49f76f 100755 --- a/artiq/gateware/targets/phaser.py +++ b/artiq/gateware/targets/phaser.py @@ -218,8 +218,6 @@ class Phaser(MiniSoC, AMPSoC): rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=32, ofifo_depth=2)) - self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels) - self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels) rtio_channels.extend(rtio.Channel.from_phy(phy) for sawg in self.ad9154.sawgs diff --git a/artiq/gateware/targets/pipistrello.py b/artiq/gateware/targets/pipistrello.py index 7dd1c01cd..6d264bad4 100755 --- a/artiq/gateware/targets/pipistrello.py +++ b/artiq/gateware/targets/pipistrello.py @@ -198,15 +198,12 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4)) - self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels) - phy = ttl_simple.ClockGen(platform.request("ttl", 15)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) phy = spi.SPIMaster(self.platform.request("pmod_extended_spi", 0)) self.submodules += phy - self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.Channel.from_phy( phy, ofifo_depth=64, ififo_depth=64))