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update release notes
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@ -6,25 +6,60 @@ Release notes
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ARTIQ-5
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-------
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* The :class:`~artiq.coredevice.ad9910.AD9910` and
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:class:`~artiq.coredevice.ad9914.AD9914` phase reference timestamp parameters
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have been renamed to ``ref_time_mu`` for consistency, as they are in machine
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units.
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* :func:`~artiq.tools.verbosity_args` has been renamed to
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:func:`~artiq.tools.add_common_args`, and now adds a ``--version`` flag.
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Highlights:
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* Performance improvements:
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- Faster RTIO event submission (1.5x improvement in pulse rate test)
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See: https://github.com/m-labs/artiq/issues/636
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- Faster compilation times (3 seconds saved on kernel compilation time on a typical
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medium-size experiment)
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See: https://github.com/m-labs/artiq/commit/611bcc4db4ed604a32d9678623617cd50e968cbf
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* Improved packaging and build system:
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- new continuous integration/delivery infrastructure based on Nix and Hydra,
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providing reproducibility, speed and independence.
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- rolling release process (https://github.com/m-labs/artiq/issues/1326).
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- firmware, gateware and device database templates are automatically built for all
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supported Kasli variants.
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- new JSON description format for generic Kasli systems.
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- Nix packages are now supported.
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- many Conda problems worked around.
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- controllers are now out-of-tree.
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- split packages that enable lightweight applications that communicate with ARTIQ,
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e.g. controllers running on non-x86 single-board computers.
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* Improved Urukul support:
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- AD9910 RAM mode.
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- Configurable refclk divider and PLL bypass.
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- More reliable phase synchronization at high sample rates.
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- Synchronization calibration data can be read from EEPROM.
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* A gateware-level input edge counter has been added, which offers higher
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throughput and increased flexibility over the usual TTL input PHYs where
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edge timestamps are not required. See :mod:`artiq.coredevice.edge_counter` for
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the core device driver and :mod:`artiq.gateware.rtio.phy.edge_counter`/
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:meth:`artiq.gateware.eem.DIO.add_std` for the gateware components.
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* With DRTIO, Siphaser uses a better calibration mechanism.
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See: https://github.com/m-labs/artiq/commit/cc58318500ecfa537abf24127f2c22e8fe66e0f8
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* Schedule updates can be sent to influxdb (artiq_influxdb_schedule).
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* Experiments can now programatically set their default pipeline, priority, and flush flag.
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* List datasets can now be efficiently appended to from experiments using
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:meth:`artiq.language.environment.HasEnvironment.append_to_dataset`.
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* The core device now supports IPv6.
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* To make development easier, the bootloader can receive firmware and secondary FPGA
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gateware from the network.
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* Python 3.7 compatibility (Nix and source builds only, no Conda).
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* Various other bugs from 4.0 fixed.
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* Preliminary Sayma v2 and Metlino hardware support.
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Breaking changes:
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* The :class:`~artiq.coredevice.ad9910.AD9910` and
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:class:`~artiq.coredevice.ad9914.AD9914` phase reference timestamp parameters
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have been renamed to ``ref_time_mu`` for consistency, as they are in machine
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units.
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* The controller manager now ignores device database entries without the
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``"command"`` key set to facilitate sharing of devices between multiple
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``command`` key set to facilitate sharing of devices between multiple
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masters.
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* The meaning of the ``-d/--dir`` and ``--srcbuild`` options of ``artiq_flash``
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has changed.
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* Experiments can now programatically set their default pipeline, priority, and flush flag.
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* Controllers for third-party devices are now out-of-tree.
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* ``aqctl_corelog`` now filters log messages below the ``WARNING`` level by default.
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This behavior can be changed using the ``-v`` and ``-q`` options like the other
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