From ee0eb238d56187e18443def09b0909a22f201893 Mon Sep 17 00:00:00 2001
From: Peter Drmota <49479443+pmldrmota@users.noreply.github.com>
Date: Tue, 11 Jan 2022 17:15:31 +0800
Subject: [PATCH] gateware.test.suservo: Fix tests for python >=3.7

Closes #1748
---
 artiq/gateware/test/suservo/test_adc.py   | 10 +++++-----
 artiq/gateware/test/suservo/test_dds.py   |  6 ++++--
 artiq/gateware/test/suservo/test_servo.py |  2 +-
 3 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/artiq/gateware/test/suservo/test_adc.py b/artiq/gateware/test/suservo/test_adc.py
index 3b31b0708..37b23305f 100644
--- a/artiq/gateware/test/suservo/test_adc.py
+++ b/artiq/gateware/test/suservo/test_adc.py
@@ -43,7 +43,7 @@ class TB(Module):
                     )
             ]
             cnv_old = Signal(reset_less=True)
-            self.sync.async += [
+            self.sync.async_ += [
                     cnv_old.eq(self.cnv),
                     If(Cat(cnv_old, self.cnv) == 0b10,
                         sr.eq(Cat(reversed(self.data[2*i:2*i + 2]))),
@@ -62,7 +62,7 @@ class TB(Module):
     def _dly(self, sig, n=0):
         n += self.params.t_rtt*4//2 # t_{sys,adc,ret}/t_async half rtt
         dly = Signal(n, reset_less=True)
-        self.sync.async += dly.eq(Cat(sig, dly))
+        self.sync.async_ += dly.eq(Cat(sig, dly))
         return dly[-1]
 
 
@@ -85,8 +85,8 @@ def main():
         assert not (yield dut.done)
         while not (yield dut.done):
             yield
-        x = (yield from [(yield d) for d in dut.data])
-        for i, ch in enumerate(x):
+        for i, d in enumerate(dut.data):
+            ch = yield d
             assert ch == i, (hex(ch), hex(i))
 
     run_simulation(tb, [run(tb)],
@@ -95,7 +95,7 @@ def main():
                 "sys":   (8, 0),
                 "adc":   (8, 0),
                 "ret":   (8, 0),
-                "async": (2, 0),
+                "async_": (2, 0),
             },
             )
 
diff --git a/artiq/gateware/test/suservo/test_dds.py b/artiq/gateware/test/suservo/test_dds.py
index e8c221f51..28e598fbc 100644
--- a/artiq/gateware/test/suservo/test_dds.py
+++ b/artiq/gateware/test/suservo/test_dds.py
@@ -44,8 +44,10 @@ class TB(Module):
                 yield
                 dat = []
                 for dds in self.ddss:
-                    v = yield from [(yield getattr(dds, k))
-                            for k in "cmd ftw pow asf".split()]
+                    v = []
+                    for k in "cmd ftw pow asf".split():
+                        f = yield getattr(dds, k)
+                        v.append(f)
                     dat.append(v)
                 data.append((i, dat))
             else:
diff --git a/artiq/gateware/test/suservo/test_servo.py b/artiq/gateware/test/suservo/test_servo.py
index c28557d89..cc1a73a2b 100644
--- a/artiq/gateware/test/suservo/test_servo.py
+++ b/artiq/gateware/test/suservo/test_servo.py
@@ -91,7 +91,7 @@ def main():
                 "sys":   (8, 0),
                 "adc":   (8, 0),
                 "ret":   (8, 0),
-                "async": (2, 0),
+                "async_": (2, 0),
             })