From ec7b2bea12e505a6ffe9c713422c96d55266ca78 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 8 Apr 2020 15:00:33 +0800 Subject: [PATCH] sayma: round FTW like Urukul in JDCGSyncDDS --- artiq/gateware/targets/sayma_amc.py | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index e469f722f..decc61640 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -250,21 +250,20 @@ class JDCGSyncDDS(Module, AutoCSR): self.sawgs = [] - ftw = round(2**len(self.coarse_ts)*9e6/150e6) + ftw = round(2**len(self.coarse_ts)*9e6/600e6) parallelism = 4 mul_1 = Signal.like(self.coarse_ts) mul_2 = Signal.like(self.coarse_ts) mul_3 = Signal.like(self.coarse_ts) self.sync.rtio += [ - mul_1.eq(self.coarse_ts*ftw), + mul_1.eq(self.coarse_ts*ftw*parallelism), mul_2.eq(mul_1), mul_3.eq(mul_2) ] phases = [Signal.like(self.coarse_ts) for i in range(parallelism)] - self.sync.rtio += [phases[i].eq(mul_3 + i*ftw//parallelism) - for i in range(parallelism)] + self.sync.rtio += [phases[i].eq(mul_3 + i*ftw) for i in range(parallelism)] resolution = 10 steps = 2**resolution