From ec62eb937352ae9559b2ae3a394273a620d1e932 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Thu, 30 Aug 2018 15:15:32 +0800
Subject: [PATCH] drtio: minor cleanup

---
 artiq/gateware/drtio/core.py                 | 9 ++++++---
 artiq/gateware/drtio/rt_controller_master.py | 2 +-
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/artiq/gateware/drtio/core.py b/artiq/gateware/drtio/core.py
index 38c6d8a2a..8eee8f4d0 100644
--- a/artiq/gateware/drtio/core.py
+++ b/artiq/gateware/drtio/core.py
@@ -128,7 +128,7 @@ class DRTIOSatellite(Module):
 
 
 class DRTIOMaster(Module):
-    def __init__(self, chanif, channel_count=1024, fine_ts_width=3):
+    def __init__(self, chanif, fine_ts_width=3):
         self.submodules.link_layer = link_layer.LinkLayer(
             chanif.encoder, chanif.decoders)
         self.comb += self.link_layer.rx_ready.eq(chanif.rx_ready)
@@ -136,9 +136,8 @@ class DRTIOMaster(Module):
         self.submodules.link_stats = link_layer.LinkLayerStats(self.link_layer, "rtio_rx")
         self.submodules.rt_packet = rt_packet_master.RTPacketMaster(self.link_layer)
         self.submodules.rt_controller = rt_controller_master.RTController(
-            self.rt_packet, channel_count, fine_ts_width)
+            self.rt_packet, fine_ts_width)
         self.submodules.rt_manager = rt_controller_master.RTManager(self.rt_packet)
-        self.cri = self.rt_controller.cri
 
         self.submodules.aux_controller = aux_controller.AuxController(
             self.link_layer)
@@ -149,3 +148,7 @@ class DRTIOMaster(Module):
                 self.rt_controller.get_csrs() +
                 self.rt_manager.get_csrs() +
                 self.aux_controller.get_csrs())
+
+    @property
+    def cri(self):
+        return self.rt_controller.cri
diff --git a/artiq/gateware/drtio/rt_controller_master.py b/artiq/gateware/drtio/rt_controller_master.py
index 786e2aa97..c3ef0214b 100644
--- a/artiq/gateware/drtio/rt_controller_master.py
+++ b/artiq/gateware/drtio/rt_controller_master.py
@@ -45,7 +45,7 @@ class RTIOCounter(Module):
 
 
 class RTController(Module):
-    def __init__(self, rt_packet, channel_count, fine_ts_width):
+    def __init__(self, rt_packet, fine_ts_width):
         self.csrs = _CSRs()
         self.cri = cri.Interface()