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kc705: fix gtx clock path durnig init

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linuswck 2023-11-07 12:04:24 +08:00 committed by Sébastien Bourdeauducq
parent 8f7d138dbd
commit ec2b86b08d
1 changed files with 4 additions and 2 deletions
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6
artiq/gateware/targets/kc705.py
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@ -273,7 +273,8 @@ class _MasterBase(MiniSoC, AMPSoC):
txout_buf = Signal()
self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf)
self.crg.configure(txout_buf, clk_sw=gtx0.tx_init.done)
self.crg.configure(txout_buf, clk_sw=self.gt_drtio.stable_clkin.storage, ext_async_rst=self.crg.clk_sw_fsm.o_clk_sw & ~gtx0.tx_init.done)
self.specials += MultiReg(self.crg.clk_sw_fsm.o_clk_sw & self.crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap")
self.comb += [
platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")),
@ -440,7 +441,8 @@ class _SatelliteBase(BaseSoC, AMPSoC):
txout_buf = Signal()
self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf)
self.crg.configure(txout_buf, clk_sw=gtx0.tx_init.done)
self.crg.configure(txout_buf, clk_sw=self.gt_drtio.stable_clkin.storage, ext_async_rst=self.crg.clk_sw_fsm.o_clk_sw & ~gtx0.tx_init.done)
self.specials += MultiReg(self.crg.clk_sw_fsm.o_clk_sw & self.crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap")
self.comb += [
platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")),